Clock purifies phaselocked loop

Clock purifies phaselocked loop

  • CN 102,177,656 B
  • Filed: 10/08/2009
  • Issued: 08/31/2016
  • Est. Priority Date: 10/08/2008
  • Status: Active Grant
First Claim
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1. an integrated circuit, it comprises:

  • Phase-locked loop pll, it has the first clock of spurious signal in order to receive owing to periodic sudden frequency hoppingSignal offer have the second clock signal of the spurious signal of minimizing, and described second clock signal is by described PLLThe integer divider ratio of the divider in loop based on described PLL and produce;

    AndA/D converter ADC, it is in order to the digitized simulation baseband signal based on described second clock signal and providesNumeral sample.

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