Correlation-based background calibration of pipelined converters with reduced power penalty

Correlation-based background calibration of pipelined converters with reduced power penalty

  • CN 102,177,657 A
  • Filed: 08/07/2009
  • Published: 09/07/2011
  • Est. Priority Date: 08/12/2008
  • Status: Active Grant
First Claim
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1. one kind provides the sub-switching stage of analog to digital converter (ADC) in response to the output signal of input signal, and it comprises:

  • Quantizer, this quantizer is connected to receiving inputted signal;

    AndRandom sequence digital to analog converter (RSDAC), this random sequence digital to analog converter is connected to random signal is injected described quantizer, and described random sequence digital to analog converter comprises many capacitive branch that are arranged in parallel;

    Wherein capacitive branch separately worked during the clock cycle of described quantizer.

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