Chip scale package and preparation method thereof

Chip scale package and preparation method thereof

  • CN 102,376,591 A
  • Filed: 08/12/2010
  • Published: 03/14/2012
  • Est. Priority Date: 08/12/2010
  • Status: Active Application
First Claim
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1. the method for making of a chip size package is characterized in that, comprising:

  • The electronic component and a hard plate of a plurality of tool relativity faces and non-acting surface are provided, and this electronic component acting surface is provided with a plurality of electronic padses;

    Be provided with soft layer on this hard plate surface;

    And this electronic component glues through its non-acting surface to be located on this soft layer;

    This electronic component of pressing makes this soft layer this electronic component of coating and exposes outside this electronic component acting surface;

    On this electronic component acting surface and soft layer, dielectric layer is set, and makes this dielectric layer form opening to expose outside this electronic pads;

    AndOn this dielectric layer, form first line layer, and make this first line layer be electrically connected to this electronic pads.

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