Array substrate and manufacturing method thereof

Array substrate and manufacturing method thereof

  • CN 102,456,620 A
  • Filed: 10/22/2010
  • Published: 05/16/2012
  • Est. Priority Date: 10/22/2010
  • Status: Active Application
First Claim
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1. the manufacturing approach of an array base palte is characterized in that, comprising:

  • On underlay substrate, form the grid metallic film;

    On said grid metallic film, apply photoresist;

    And adopt the duotone mask plate that photoresist is carried out exposure imaging, formation comprises first thickness area, second thickness area and removes the photoresist pattern in zone fully that the photoresist pattern of said first thickness area is positioned at the grid region top at least;

    The photoresist pattern of said second thickness area is positioned at grid line lead-in wire join domain top, and first thickness is less than second thickness;

    Carry out etching, etch away and remove the corresponding grid metallic film in zone fully, form the pattern that comprises grid line, gate electrode and grid line lead-in wire, and remove photoresist according to the first thickness ashing of the said first thickness area photoresist;

    Metallic film is leaked in successive sedimentation gate insulation layer film, active layer film and source on the underlay substrate that forms above-mentioned pattern;

    On said source leakage metallic film, apply photoresist;

    And adopt the duotone mask plate that photoresist is carried out exposure imaging;

    Formation comprises the 3rd thickness area, the 4th thickness area and removes the photoresist pattern in zone fully;

    The photoresist pattern of said the 3rd thickness area is positioned at source-drain electrode zone and data cable lead wire join domain top at least, and the photoresist pattern of said the 4th thickness area is positioned at the channel region top, and the 4th thickness is less than the 3rd thickness;

    Carry out etching, etch away and remove the corresponding semiconductor layer film in zone, doped semiconductor layer film and source leakage metallic film fully, and remove photoresist according to the 4th thickness ashing of said the 4th thickness area photoresist;

    Carry out etching, metallic film and part active layer film are leaked in the source that etches away channel region, form the TFT raceway groove;

    And with grid metallic film and photoresist lift off above remaining photoresist pattern and the grid line lead-in wire join domain;

    On the underlay substrate that forms above-mentioned pattern, form pixel electrode through photoetching process.

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