Array substrate and manufacturing method thereof

Array substrate and manufacturing method thereof

  • CN 102,456,620 B
  • Filed: 10/22/2010
  • Issued: 04/15/2015
  • Est. Priority Date: 10/22/2010
  • Status: Active Grant
First Claim
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1. a manufacture method for array base palte, is characterized in that, comprising:

  • Underlay substrate is formed grid metallic film, described grid metallic film applies photoresist, and adopt duotone mask plate to carry out exposure imaging to photoresist, form the photoetching agent pattern comprising the first thickness area, the second thickness area and remove region completely, the photoetching agent pattern of described first thickness area is at least positioned at above grid region, the photoetching agent pattern of described second thickness area is positioned at above grid line lead-in wire join domain, and the first thickness is less than the second thickness;

    Etch, etch away and remove grid metallic film corresponding to region completely, form the pattern comprising grid line, gate electrode and grid line lead-in wire, and remove photoresist according to the first thickness ashing of described first thickness area photoresist;

    Successive sedimentation gate insulation layer film on the underlay substrate forming above-mentioned pattern, active layer film and source and drain metallic film, described source and drain metallic film applies photoresist, and adopt duotone mask plate to carry out exposure imaging to photoresist, formation comprises the 3rd thickness area, 4th thickness area and remove the photoetching agent pattern in region completely, the photoetching agent pattern of described 3rd thickness area is at least positioned at above source-drain electrode region and data cable lead wire join domain, the photoetching agent pattern of described 4th thickness area is positioned at above channel region, and the 4th thickness is less than the 3rd thickness,Etch, etch away and remove region corresponding semiconductor layer film, doped semiconductor layer film and source and drain metallic film completely, and remove photoresist according to the 4th thickness ashing of described 4th thickness area photoresist;

    Etch, etch away source and drain metallic film and the part active layer film of channel region, form TFT raceway groove;

    And by the grid metallic film above remaining photoetching agent pattern and grid line lead-in wire join domain and photoresist lift off;

    The underlay substrate forming above-mentioned pattern forms pixel electrode by photoetching process.

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