A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof

A kind of low temperature polycrystalline silicon tft array substrate and manufacture method thereof

  • CN 102,683,338 B
  • Filed: 09/13/2011
  • Issued: 08/24/2016
  • Est. Priority Date: 09/13/2011
  • Status: Active Grant
First Claim
Patent Images

1. a low temperature polycrystalline silicon tft array substrate, it is characterised in that including:

  • Substrate;

    It is formed with polysilicon layer;

    It is formed with source electrode, drain electrode and polysilicon semiconductor active layer by a patterning processes;

    ItAfter, the part between the source of described polysilicon semiconductor active layer, drain electrode is doped process,Described source electrode, drain electrode is made to constitute TFT zone with described polysilicon semiconductor active layer;

    It is formed with gate insulation layer in described source electrode, drain electrode;

    Grid, grid line it is formed with on described gate insulation layer;

    It is formed with protective layer on described grid, grid line;

    Being formed with pixel electrode layer on described protective layer, described pixel electrode layer is described by being positioned atVia on protective layer, gate insulation layer is connected with described drain electrode.

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