Multi-level hierarchical routing matrices for pattern-recognition processors

Multi-level hierarchical routing matrices for pattern-recognition processors

  • CN 102,713,936 A
  • Filed: 12/07/2010
  • Published: 10/03/2012
  • Est. Priority Date: 12/15/2009
  • Status: Active Application
First Claim
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1. device, it comprises:

  • The pattern identification processor, it comprises;

    A plurality of logical. group, wherein each group comprises one or more feature units, wherein said one or more feature units of each group are coupled to the first via by line through first connection;

    A plurality of logical lines, wherein each row comprises one or more in said a plurality of group, wherein said one or more groups of each row connect through second and are coupled to the secondary route line;

    AndA plurality of logical blocks, wherein each piece comprises one or more in said a plurality of row, wherein said one or more of each piece worked and the 3rd connect and be coupled to Third Road by line;

    Wherein said a plurality of connect through the 4th and to be coupled to the 4th route line.

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