For the bang-bang phase discriminator of half rate clock data recovery circuit

For the bang-bang phase discriminator of half rate clock data recovery circuit

  • CN 102,801,414 B
  • Filed: 08/23/2012
  • Issued: 03/30/2016
  • Est. Priority Date: 08/23/2012
  • Status: Active Grant
First Claim
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1. , for the bang-bang phase discriminator of half rate clock data recovery circuit, comprise sample circuit trigger module, judging module, two along trigger module;

  • Sample circuit trigger module respectively under the control of the orthogonal each other clock pulse clk0 in four roads, clk90, clk180, clk270 to sampling input data, the sampled data under the sampled data respectively under output clock pulse clk0, the sampled data under clock pulse clk90, the sampled data under clock pulse clk180, clock pulse clk270;

    The rising edge of described clock pulse clk90 postpones T/4 relative to clock pulse clk0 and arrives, the rising edge of described clock pulse clk180 postpones T/4 relative to clock pulse clk90 and arrives, the rising edge of described clock pulse clk270 postpones T/4 relative to clock pulse clk180 and arrives, and T is the cycle of clock pulse clk0, clk90, clk180, clk270;

    It is characterized in that,Also comprise re-synchronization trigger module, sampled data under the clock pulse clk0 exported by sample circuit trigger module under clock pulse clk180 controls, the sampled data under clock pulse clk90 carry out synchronism output, and the sampled data under the clock pulse clk180 exported by sample circuit trigger module under clock pulse clk0 controls, the sampled data under clock pulse clk270 carry out synchronism output;

    Sampled data under clock pulse clk0 after the process of re-synchronization trigger module and the sampled data under the clock pulse clk90 after the process of re-synchronization trigger module are carried out XOR by judging module, sampled data under clock pulse clk180 after the process of re-synchronization trigger module and the sampled data under the clock pulse clk270 after the process of re-synchronization trigger module are carried out XOR, sampled data under the clock pulse clk180 directly export the sampled data under the clock pulse clk90 from re-synchronization trigger module and sample circuit trigger module carries out XOR, by the sampled data under the clock pulse clk270 from re-synchronization trigger module with carry out XOR from the sampled data under the clock pulse clk0 of sample circuit trigger module, obtain respectively adjudicating index signal Up1, Up2, Dn1, Dn2,Two reception along trigger module adjudicates enable couple of index signal Up1, Up2 along trigger module output UP signal, and judgement index signal Dn1, Dn2 is enable two along trigger module output DN signal;

    Two along trigger module reception judgement index signal Up1, enable couple of judgement index signal Dn1 along trigger module synchronism output coupling UP signal and DN signal under clock pulse clk270 control, under clock pulse clk90 control, two reception along trigger module adjudicates index signal Up2, enable couple of judgement index signal Dn2 along trigger module synchronism output coupling UP signal and DN signal.

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