Shift register unit, shift register and display device

Shift register unit, shift register and display device

  • CN 103,456,365 A
  • Filed: 08/30/2013
  • Published: 12/18/2013
  • Est. Priority Date: 08/30/2013
  • Status: Active Application
First Claim
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1. a shift register cell, is characterized in that:

  • comprise the first transistor, transistor seconds, the 3rd transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and memory capacitance;

    Wherein,The grid of described the first transistor is connected the input signal end with first utmost point, and second utmost point connects upper drawknot point;

    The grid of described transistor seconds connects the reset signal end, and first utmost point connects described upper drawknot point, and second utmost point connects the datum line;

    The described the 3rd transistorized grid connects described upper drawknot point, and first utmost point connects the first clock signal, and second utmost point connects output signal end;

    Described the 5th transistorized grid connects drop-down node, and first utmost point connects described output signal end, and second utmost point connects described datum line;

    The described the 6th transistorized grid connects described drop-down node, and first utmost point connects described upper drawknot point, and second utmost point connects described datum line;

    Described the 7th transistorized grid is connected the second clock signal with first utmost point, and second utmost point connects described drop-down node;

    The described the 8th transistorized grid connects the input signal end, and first utmost point connects described drop-down node, and second utmost point connects described datum line;

    First utmost point of described memory capacitance connects described upper drawknot point, and second utmost point connects described output signal end.

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