Apparatus and method for implementing a multi-level memory hierarchy over common memory channels

Apparatus and method for implementing a multi-level memory hierarchy over common memory channels

  • CN 103,946,826 A
  • Filed: 09/30/2011
  • Published: 07/23/2014
  • Est. Priority Date: 09/30/2011
  • Status: Active Application
First Claim
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1. a computer system, comprising:

  • Processor, described processor has a plurality of for carrying out the core of instruction deal with data and one or more for carry out the processor high speed buffer memory of high-speed cache instruction and data according to the first cache management strategy;

    First memory passage, it comprises the first group address/control and the data circuit that is coupled to described processor;

    Second memory passage, it comprises the second group address/control and the data circuit that is coupled to described processor;

    First order first memory and first order second memory, first group of characteristic respectively with associated, first group of characteristic comprises the first read access speed and the first write access speed, first order first memory is coupled to first memory passage, and first order second memory is coupled to second memory passage;

    AndSecond level first memory is coupled to first memory passage by correspondence, and second level second memory is coupled to second memory passage by correspondence, second level first memory and second level second memory have second group of characteristic of associated, second group of characteristic comprises the second read access speed and the second write access speed, the second read access speed is compared lower with the first read access speed or the first write access speed respectively with at least one in the second write access speed, non-volatile, if power supply is removed, second level first memory and second level second memory are preserved content, wherein at least a portion of first order first memory is configured to for being stored in the high-speed cache of the instruction and data of second level first memory, and at least a portion of first order second memory is configured to for being stored in the high-speed cache of the instruction and data of second level second memory.

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