Multi-core interconnect in a network processor

Multi-core interconnect in a network processor

  • CN 103,959,261 A
  • Filed: 10/29/2012
  • Published: 07/30/2014
  • Est. Priority Date: 10/31/2011
  • Status: Active Application
First Claim
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1. the computer system on computer chip, comprising:

  • An interconnection circuit;

    Many rambus, every bus is connected to one group of corresponding a plurality of processor cores on this interconnection circuit;

    AndA high-speed cache, is divided into a plurality of, and wherein each is connected on this interconnection circuit by an independent bus;

    This interconnection circuit is configured for a plurality of requests that receive from the plurality of processor cores is distributed between the plurality of.

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