Conditional link for direct memory access controller

Conditional link for direct memory access controller

  • CN 104,133,790 B
  • Filed: 03/14/2014
  • Issued: 10/01/2019
  • Est. Priority Date: 03/14/2013
  • Status: Active Grant
First Claim
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1. a kind of direct memory access (DMA) controller, comprising:

  • Bus control unit with system bus interface and is configured to read mould from memory location via system bus interfaceFormula;

    Model comparision logic is configured to the mode of reading compared at least one preassigned pattern;

    AndControl logic is configured to cause bus control unit to pass through system bus if the mode read is matched with preassigned patternInterface handles first condition link, and is further configured to do not having if the mode and preassigned pattern difference readBus control unit is caused to handle second condition link by system bus interface in the case where generating interruption.

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