Inverted LED chip with high light emitting efficiency and LED device and manufacturing method of inverted LED chip with high light emitting efficiency

Inverted LED chip with high light emitting efficiency and LED device and manufacturing method of inverted LED chip with high light emitting efficiency

  • CN 104,134,734 A
  • Filed: 08/01/2014
  • Published: 11/05/2014
  • Est. Priority Date: 08/01/2014
  • Status: Active Application
First Claim
Patent Images

1. a flip LED chips, comprise epitaxial substrate, P surface electrode, N surface electrode, be superimposed on epitaxial substrate upper surface N-type epitaxial loayer, be superimposed on N-type epitaxial loayer upper surface luminescent layer, be superimposed on the P type epitaxial loayer of luminescent layer upper surface, it is characterized in that, described P type epitaxial loayer offers the first shrinkage pool on it, and the first shrinkage pool penetrates described luminescent layer downwards and extends to described N-type epitaxial loayer;

  • At P type epitaxial loayer upper surface, be superimposed with a P contact metal layer, and the coincident of the edge of P contact metal layer and P type epitaxial loayer, P type epitaxial loayer and the P contact metal layer of stack form the first overlaying structure mutually;

    Described its upper surface of the first overlaying structure is superimposed with P block protective layer, and the lower surface area coverage of P block protective layer is consistent with the upper surface area of P type epitaxial loayer;

    N-type epitaxial loayer, luminescent layer, P type epitaxial loayer, P contact metal layer and P block protective layer superpose successively and form the second overlaying structure, its surface of exposing of described the second overlaying structure is provided with insulating barrier, and the insulating barrier corresponding with the bottom position of described the first shrinkage pool is partly provided with the first through hole, be partly provided with the second through hole with insulating barrier corresponding to P block protective layer upper surface;

    Described N surface electrode is electrically connected to N-type epitaxial loayer by described the first through hole, and described P surface electrode is electrically connected to P block protective layer by described the second through hole.

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