Configurable multi-bit key output TVD-PUFs (Threshold Variation Delay-Physical Unclonable functions) circuit

Configurable multi-bit key output TVD-PUFs (Threshold Variation Delay-Physical Unclonable functions) circuit

  • CN 104,320,246 A
  • Filed: 09/22/2014
  • Published: 01/28/2015
  • Est. Priority Date: 09/22/2014
  • Status: Active Application
First Claim
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1. the multidigit key of a configurable exports TVD-PUFs circuit, comprise data input module, controller, shift register, decoder, n PUFs element circuit and output module, the input access external data of described data input module, the output of described data input module is connected with the input of described controller, the output of described controller is connected with the input of described shift register, the output of described shift register is connected with the input of described decoder, it is characterized in that described PUFs element circuit comprises i position threshold deviation delay circuit and decision device, described threshold deviation delay circuit is made up of two delay cells, two delay cells are respectively the first delay cell and the second delay cell,Described delay cell comprises the first PMOS, second PMOS, 3rd PMOS, 4th PMOS, first NMOS tube, second NMOS tube, 3rd NMOS tube, 4th NMOS tube and inverter, the source electrode of the first described PMOS and the source electrode of the 4th described PMOS all access power supply, the drain electrode of the first described PMOS is connected with the source electrode of the second described PMOS, the drain electrode of the second described PMOS, the drain electrode of the second described NMOS tube, the drain electrode of the 4th described PMOS is connected with the drain electrode of the 4th described NMOS tube and its link is the output of described delay cell, the source electrode of the second described NMOS tube is connected with the drain electrode of the first described NMOS tube, the source electrode of the first described NMOS tube and the source grounding of the 4th described NMOS tube, the grid of the first described PMOS, the grid of the first described NMOS tube is connected with the input of described inverter and its link is the control end of described delay cell, the grid of the second described PMOS, the grid of the second described NMOS tube, the source electrode of the 3rd described NMOS tube is connected with the drain electrode of the 3rd described PMOS and its link is the input of described delay cell, the grid of the 3rd described PMOS, the grid of the 3rd described NMOS tube is connected with the output of described inverter, the source electrode of the 3rd described PMOS is connected with the grid of the 4th described PMOS, the drain electrode of the 3rd described NMOS tube is connected with the grid of the 4th described NMOS tube,The control end of the first described delay cell is connected with the control end of the second described delay cell and its link is the control end of described threshold deviation delay circuit, the input of the first described delay cell is the first input end of described threshold deviation delay circuit, the output of the first described delay cell is the first output of described threshold deviation delay circuit, the input of the second described delay cell is the second input of described threshold deviation delay circuit, the output of the second described delay cell is the second output of described threshold deviation delay circuit, the first input end of the 1st threshold deviation delay circuit is connected with the second input and its link is the input of described PUFs element circuit, the first input end of the first output and jth+1 threshold deviation delay circuit of jth position threshold deviation delay circuit is connected, second input of the second output and jth+1 threshold deviation delay circuit of jth position threshold deviation delay circuit is connected, first output of i-th threshold deviation delay circuit is connected with the input of the second output with described decision device, the output of described decision device is the output of described PUFs element circuit, the n position output of the TVD-PUFs circuit described in output composition of n PUFs element circuit, the n position output of described TVD-PUFs circuit is connected with the input of described output module, the output of described output module exports key, the control end being positioned at the threshold deviation delay circuit of identical bits in n PUFs element circuit connects the control end that its link is described TVD-PUFs circuit, described TVD-PUFs circuit has i control end,In data input module described in external data input, described controller generates i position control signal, the operating state of i position threshold deviation delay circuit in control n PUFs element circuit in n control end of the TVD-PUFs circuit of i position control signal after shift register and decoder process described in one_to_one corresponding input, i threshold deviation delay circuit of described PUFs element circuit is made to be operated in NMOS tube delayed mode, PMOS delayed mode or inverter delay pattern, when changing the external data in the data input module described in input, the i position control signal that described controller generates changes thereupon, the signal that the i position control signal that controller described thus exports is inputted by described data input module is determined, when the external data of described data input module input changes, the i position control signal that described controller exports changes, the operating state of the i position threshold deviation delay circuit in described PUFs element circuit changes, the process deviation produced in described PUFs element circuit changes, the key that described TVD-PUFs circuit exports is reconstructed, wherein n >

  • =2, i >

    =2, j=1 ..., i-1.

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