Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same

Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same

  • CN 104,850,672 A
  • Filed: 04/22/2014
  • Published: 08/19/2015
  • Est. Priority Date: 02/18/2014
  • Status: Active Application
First Claim
Patent Images

1. a method, comprising:

  • The layout of integrated circuit (IC) design is provided;

    Generate multiple multigraph patterning by processor by described layout to decompose, wherein, each the including in described multiple multigraph patterning decomposition is allocated to the first mask of multigraph patterning mask set and the pattern of the second mask;

    Determine the maximum mask displacement between described first mask and described second mask;

    AndUse by the one or more mask displacements in described maximum mask displacement limited range, each worst condition performance number in decomposing described multiple multigraph patterning emulates.

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