Method for manufacturing semiconductor device

Method for manufacturing semiconductor device

  • CN 104,882,413 B
  • Filed: 02/27/2015
  • Issued: 12/18/2020
  • Est. Priority Date: 02/28/2014
  • Status: Active Grant
First Claim
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1. A method of manufacturing a semiconductor device comprising a memory cell of a non-volatile memory, the method comprising the steps of:

  • (a) providing a semiconductor substrate;

    (b) forming a first dummy gate electrode over the semiconductor substrate via a first insulating film;

    (c) forming a first gate electrode for the memory cell over the semiconductor substrate via a second insulating film having an internal charge storage portion such that the first gate electrode for the memory cell is adjacent to the first dummy gate electrode;

    (d) forming a first interlayer insulating film so as to cover the first dummy gate electrode and the first gate electrode therewith;

    (e) polishing the first interlayer insulating film to expose the first dummy gate electrode;

    (f) after said step (e), removing said first dummy gate electrode; and

    (g) forming a second gate electrode for the memory cell in a first trench that is an area resulting from the removing of the first dummy gate electrode in the step (f),wherein the second gate electrode is a metal gate electrode,wherein the first gate electrode formed in said step (c) has a height lower than that of said first dummy gate electrode, andwherein, in the step (e), the first gate electrode is not exposed;

    after said step (c) and before said step (d), further comprising the steps of;

    (c7) forming, over the semiconductor substrate, a second dummy gate electrode via a third insulating film, and a fourth gate electrode for MISFETs other than the MISFET of the memory cell via a fourth insulating film;

    wherein, in the step (g), the second gate electrode is formed in the first trench, and a third gate electrode for MISFETs other than MISFETs of the memory cell is formed in a second trench which is an area resulting from the removal of the second dummy gate electrode in the step (f);

    wherein, in the step (f), the fourth gate electrode is not removed.

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