Radio frequency switch used for controlling sending and receiving path switching, radio frequency system and operation method

Radio frequency switch used for controlling sending and receiving path switching, radio frequency system and operation method

  • CN 104,935,316 A
  • Filed: 03/21/2014
  • Published: 09/23/2015
  • Est. Priority Date: 03/21/2014
  • Status: Active Application
First Claim
Patent Images

1. a switch, it is characterized in that, described switch comprises the first device (200), one NMOSFET(M22), second device (210), 2nd NMOS FET(M26), receiver enable node (RXEN), transmitter enable node (TXEN), first resistance (R20), second resistance (R21), 3rd resistance (R22), 4th resistance (R23), 5th resistance (R24), 6th resistance (R25), 7th resistance (R26), 8th resistance (R27), 9th resistance (R28), tenth resistance (R29), voltage source (VC), first electric capacity (C20) and the second electric capacity (C22),Wherein, first pole of described first device is connected with transmitter port, second pole of described first device is connected with receiver enable node via described first resistance, 3rd pole of described first device is connected to ground via described first electric capacity, 4th pole of described first device is connected to ground via described second resistance, and the 3rd pole of described first device is also connected with described voltage source via described 9th resistance;

  • The drain electrode of a described NMOS FET is connected with antenna port, the grid of a described NMOS FET is connected with transmitter enable node via described 3rd resistance, the source electrode of a described NMOS FET is connected with described transmitter port, and the body end of a described NMOS FET is connected to ground via described 4th resistance;

    First pole of described second device is connected with described antenna port, second pole of described second device is connected with described receiver enable node via described 5th resistance, 3rd pole of described second device is connected with receiver port, and the 4th pole of described second device is connected to ground via described 6th resistance;

    The drain electrode of described 2nd NMOS FET is connected with described receiver port, the grid of described 2nd NMOSFET is connected with described transmitter enable node via described 7th resistance, the source electrode of described 2nd NMOSFET is connected to ground via described second electric capacity, the body end of described 2nd NMOS FET is connected to ground via described 8th resistance, and the source electrode of described 2nd NMOS FET is also connected with described voltage source via described tenth resistance.

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