Strain Ge groove-type gate CMOS (Complementary Metal Oxide Semiconductor) integrated device manufacturing method and CMOS integrated device thereof

Strain Ge groove-type gate CMOS (Complementary Metal Oxide Semiconductor) integrated device manufacturing method and CMOS integrated device thereof

  • CN 105,118,809 A
  • Filed: 08/28/2015
  • Published: 12/02/2015
  • Est. Priority Date: 08/28/2015
  • Status: Active Application
First Claim
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1. strain a Ge grooved grid CMOS integrated device preparation method, it is characterized in that, comprise step:

  • A () chooses SOI substrate;

    B () be grow sige layers, strained ge layer and strain Si cap layers in described SOI substrate, to form NMOS active area and PMOS active area;

    C () adopts etching technics to form isolated groove between described NMOS active area and described PMOS active area;

    D NMOS area of grid etching formation two inverted trapezoidal grooves that () utilizes dry etch process to specify in described NMOS surfaces of active regions;

    E (), in described NMOS active area and described PMOS surfaces of active regions growth oxide layer, utilizes dry etch process to etch the described oxide layer of described PMOS surfaces of active regions subregion, forms the gate dielectric layer of described PMOS;

    F () adopts ion implantation technology to form PMOS source drain region to described PMOS surfaces of active regions implanting p-type ion;

    G () forms described PMOS grid at the gate dielectric layer superficial growth grid material of described PMOS;

    H () grows grid material to form described NMOS grid at described NMOS area of grid;

    And(i) metalized, and photoetching drain lead, source lead and grid lead, the described strain Ge grooved grid CMOS integrated device of final formation.

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