Preparation method of strain SiGe channel groove type grid CMOS integrated device based on GOI

Preparation method of strain SiGe channel groove type grid CMOS integrated device based on GOI

  • CN 105,140,185 A
  • Filed: 08/28/2015
  • Published: 12/09/2015
  • Est. Priority Date: 08/28/2015
  • Status: Active Application
First Claim
Patent Images

1. , based on a preparation method for the strain SiGe channel grooved grid CMOS integrated device of GOI, it is characterized in that, comprise step:

  • A () chooses GOI substrate;

    B () in described GOI Grown N-type strained sige layer, and adopts ion implantation technology to carry out the N-type strained sige layer of the certain doping content of N-type doping formation;

    In described N-type strained sige layer superficial growth one deck N-type Si cap layers, to form enhancement mode NMOS active area and depletion type PMOS active area;

    C () adopts etching technics to form isolated groove between described enhancement mode NMOS active area and described depletion type PMOS active area;

    D () photoetching forms enhancement mode NMOS gate regions, adopt etching technics to form two inverted trapezoidal groove on surface, described enhancement mode NMOS gate regions;

    E (), in described enhancement mode NMOS active area and described depletion type PMOS surfaces of active regions growth oxide layer, utilizes dry etch process to etch the described oxide layer of described depletion type PMOS surfaces of active regions subregion, forms depletion type PMOS gate dielectric layer;

    F () adopts ion implantation technology to form depletion type PMOS source drain region to described depletion type PMOS surfaces of active regions implanting p-type ion;

    G () forms depletion type PMOS grid at the gate dielectric layer superficial growth grid material of described depletion type PMOS;

    H () grows grid material to form enhancement mode NMOS grid in described enhancement mode NMOS gate regions;

    And(i) metalized, and photoetching drain lead, source lead and grid lead, the described strain SiGe channel grooved grid CMOS integrated device based on GOI of final formation.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×