Multichannel HDLC data processing device based on FPGA and FIFO chip

Multichannel HDLC data processing device based on FPGA and FIFO chip

  • CN 105,302,753 B
  • Filed: 11/13/2015
  • Issued: 06/16/2020
  • Est. Priority Date: 11/13/2015
  • Status: Active Grant
First Claim
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1. The utility model provides a multichannel HDLC data processing apparatus based on FPGA and FIFO chip, includes receiving direction device and transmitting direction device, and wherein, receiving direction device includes first RHDDLC module to Nth RHDDLC module and first CRC check module to Nth CRC check module, and transmitting direction device includes first THDLC module to Nth THDLC module and first CRC generation module to Nth CRC generation module, its characterized in that:

  • the receiving direction device also comprises a first receiving RAM controller to an Nth receiving RAM controller, a first receiving RAM to an Nth receiving RAM, a receiving FIFO controller and a receiving FIFO chip, and the sending direction device also comprises a first sending RAM controller to an Nth sending RAM controller, a first sending RAM to an Nth sending RAM, a sending FIFO controller and a sending FIFO chip;

    the receiving direction is as follows;

    the first RHDLC module to the Nth RHDLC module respectively receive external HDLC data information and clock information, the HDLC data information is respectively subjected to frame head detection, zero deletion operation and frame tail detection, serial data are converted into parallel data, and the parallel data are output to the first CRC check module to the Nth CRC check module in a one-to-one correspondence mode;

    the first CRC checking module to the Nth CRC checking module carry out CRC checking on the parallel data by adopting parallel XOR operation, and discard the parallel data according to the checking result or output the parallel data to the first receiving RAM controller to the Nth receiving RAM controller in a one-to-one correspondence manner;

    the first receiving RAM controller to the Nth receiving RAM controller respectively write the parallel data into the first receiving RAM to the Nth receiving RAM in a one-to-one correspondence mode according to the states of receiving the first receiving RAM to the Nth receiving RAM;

    the first receiving RAM to the Nth receiving RAM respectively cache the received parallel data;

    the receiving FIFO controller writes the cache data in the first receiving RAM to the Nth receiving RAM into the receiving FIFO chip according to the states of the first receiving RAM to the Nth receiving RAM and the state of the receiving FIFO chip;

    the receiving FIFO chip is used for caching the received parallel data;

    the sending direction is as follows;

    the transmission FIFO chip is used for caching data to be transmitted;

    the transmission FIFO controller reads data to be transmitted from the transmission FIFO chip according to the states of the first transmission RAM to the Nth transmission RAM and the states of the transmission FIFO chip and writes the data to be transmitted into the first transmission RAM to the Nth transmission RAM in a one-to-one correspondence manner;

    the first sending RAM to the Nth sending RAM are used for respectively caching the received data to be sent;

    the first sending RAM controller to the Nth sending RAM controller are used for correspondingly reading frame data in the first sending RAM to the Nth sending RAM and transmitting the frame data to the first CRC generation module to the Nth CRC generation module in a one-to-one correspondence manner;

    the first CRC generation module to the Nth CRC generation module are used for respectively carrying out CRC generation operation on frame data and generating CRC check codes, and sending the frame data and the CRC check codes to the first THDLC module to the Nth THDLC module in a one-to-one correspondence mode;

    the first THDLC module to the Nth THDLC module are used for respectively carrying out frame head inserting identification, zero inserting operation, CRC code inserting operation and frame inserting tail identification operation on a frame of data to form parallel data, converting the parallel data into serial data and then sending the serial data to the outside.

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