Chip device and bump configuration method thereof

Chip device and bump configuration method thereof

  • CN 105,374,694 B
  • Filed: 12/04/2015
  • Issued: 09/01/2020
  • Est. Priority Date: 12/04/2015
  • Status: Active Grant
First Claim
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1. A chip apparatus, comprising:

  • a plurality of bumps, comprising;

    a plurality of first bumps disposed on a top metal layer of the chip device for supplying a first voltage to a plurality of integrated circuits in the chip device;

    a plurality of second bumps disposed on the top metal layer of the chip device for supplying a second voltage to the integrated circuit; and

    a substrate electrically connected to the first bump and the second bump,wherein the plurality of bumps are arranged in a plurality of rows and a plurality of columns, the column spacing of the plurality of columns is equal, the row spacing of the plurality of rows is equal,wherein two adjacent bumps in each row of the plurality of bumps are the first bump and the second bump respectively,wherein the first of each row and the first of the adjacent row in the plurality of bumps are the first bump and the second bump respectively,wherein a first one of the each column of the plurality of bumps is aligned with a first one of the adjacent column,the integrated circuit is arranged between the first bump and the second bump, so that the distance from the integrated circuit to the nearest first bump is equal to the distance from the integrated circuit to the nearest second bump.

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