Transmission system for converting 9-channel coder signals into 1000Mbps PHY signals

Transmission system for converting 9-channel coder signals into 1000Mbps PHY signals

  • CN 105,554,034 A
  • Filed: 02/05/2016
  • Published: 05/04/2016
  • Est. Priority Date: 02/05/2016
  • Status: Active Application
First Claim
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1. a road code device signal turns the transmission system of 1000MbpsPHY signal, it is characterized in that:

  • comprise PHY chip circuit U 1, U2, digital light electric coupling U3 ~ U11,485 transceiver U12 ~ U20, RJ45 is with isolating transformer socket J1, J2, FPGA chip circuit (1), EPCS configuring chip circuit (2), Jtag interface (3) and SM-6P-PCB socket J3 ~ J11The two-way MII digital signal I/O of FPGA chip circuit (1) is connected with the MII digital signal input/output terminal of PHY chip circuit U 1, U2 respectively;

    The differential data signals I/O of PHY chip circuit U 1, U2 is connected to RJ45 and is with on isolating transformer socket J1, J2;

    the first via 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U12 by digital light electric coupling U3, second tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U13 by digital light electric coupling U4,3rd tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U14 by digital light electric coupling U5,4th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U15 by digital light electric coupling U6,5th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U16 by digital light electric coupling U7,6th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U17 by digital light electric coupling U8,7th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U18 by digital light electric coupling U9,8th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U19 by digital light electric coupling U10,9th tunnel 485 digital signal input/output terminal of FPGA chip circuit (1) is connected with the digital signal I/O of 485 transceiver U20 by digital light electric coupling U11, the serial date transfer output of FPGA chip circuit (1) is connected with the serial data I/O of EPCS configuring chip circuit (2), the Jtag test data I/O of FPGA chip circuit (1) is connected on Jtag interface (3), the 485 communication data I/Os of 485 transceiver U12 ~ U20 connect SM-6P-PCB socket J3 ~ J11 respectively, 485 transceiver U12 ~ U20 adopt isolation power supply,Can 1-10 road signal be transferred to PHY Signal transmissions.

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