Delayed ion extraction module suitable for time of-flight mass spectrometer

Delayed ion extraction module suitable for time of-flight mass spectrometer

CN
  • CN 105,789,019 B
  • Filed: 05/23/2016
  • Issued: 08/01/2017
  • Est. Priority Date: 05/23/2016
  • Status: Active Grant
First Claim
Patent Images

1. a kind of delayed ion extraction module suitable for time of-flight mass spectrometer, including for receiving the letter of Laser synchronisation signalNumber circuit is caught, the output end of the signal capture circuit is connected with the signal input part of signal broadening circuit, the signal exhibitionThe output end of stretch circuit and the signal input part of signal delay circuit are connected, and the output end of the signal delay circuit is touched by firstSignalling output end and the second trigger signal output end composition;

  • It is characterized in that:

    The signal capture circuit is made up of triode Q1 and schmitt inverter;

    The triode Q1 base stages are through resistance R1 with swashingLight device synchronous signal output end is connected, and triode Q1 grounded emitters, triode Q1 colelctor electrodes are connecing power supply just through resistance R2 all the wayPole, another road is connected with the signal input part of the schmitt inverter;

    The signal broadening circuit is made up of two monostable flipflops U2A, U2B and d type flip flop U3;

    The d type flip flop U3'"'"'sInput end of clock CLK is connected with the signal output part of the schmitt inverter;

    D type flip flop U3 inverse output terminal, data are defeatedEnter to hold D to be connected with each other;

    D type flip flop U3 forward direction output end Q are connected with the positive triggering input B of the monostable flipflop U2A;

    Monostable flipflop U2A removing termination high level VCC, negative triggering input A meets low level GND, external capacitor endCext connects high level VCC, outer meeting resistance/capacitance terminal Rext/Cext and the resistance R3 low electricity by electric capacity C1, resistance R3Position end connection, positive pulse output end Q is connected with monostable flipflop U2B negative triggering input A;

    Monostable flipflop U2B positive triggering input B and removing end connect high level VCC, negative pulse output end and d type flip flopU3 reset terminal CLR is connected;

    Monostable flipflop U2B external capacitor end Cext connects high level by electric capacity C2, resistance R4VCC, outer meeting resistance/capacitance terminal Rext/Cext is connected with the cold end of the resistance R4;

    The signal delay circuit is made up of programmable time chip and two with door U5A, U5B;

    The programmable time chipSerial programming selection termination high level, select serial mode, output mode selection end MS connect low level, i.e.,:

    Output signal withInput signal polarity is identical;

    The signal input part IN of programmable time chip and monostable flipflop in the signal broadening circuitU2A positive triggering input B connections;

    The signal output part OUT of programmable time chip respectively with described in two with door U5A, U5BFirst input end connection, two and door U5A, U5B the second input meets high level VCC.

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