Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration

Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration

  • CN 105,845,168 A
  • Filed: 02/01/2016
  • Published: 08/10/2016
  • Est. Priority Date: 02/04/2015
  • Status: Active Application
First Claim
Patent Images

1. an integrated circuit, comprising:

  • Memory cell;

    Bit line, described bit line is coupled to described memory cell;

    Precharge transistor, described precharge transistor is coupled to described bit line;

    AndFor the decoder addressing described memory cell, wherein said decoder determined in the decoding time periodWhether memory cell described in period is chosen, and wherein described precharge during the described decoding time periodTransistor is disconnected.

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