Grounding dummy gate in scaled layout design

Grounding dummy gate in scaled layout design

  • CN 105,981,157 B
  • Filed: 01/08/2015
  • Issued: 12/08/2020
  • Est. Priority Date: 02/14/2014
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor device, comprising:

  • a dummy gate in an active region of the semiconductor device;

    a first active contact adjacent to the dummy gate;

    a dielectric layer on the dummy gate and the first active contact, the dielectric layer having an opening formed therein;

    a first isolation layer deposited on sidewalls of the opening;

    a first stacked contact formed in the opening, the first stacked contact being electrically coupled to the first active contact;

    a capping layer deposited on a surface of the first stacked contact opposite the first active contact, the first isolation layer on sidewalls electrically isolating the first stacked contact from the dummy gate; and

    a first via through the dielectric layer, the first via landing on the dummy gate and directly landing on the surface of the first stacked contact through a portion of the capping layer to electrically couple the first stacked contact and the first active contact to the dummy gate to ground the dummy gate.

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