RM logic circuit delay optimization method in unit delay model

RM logic circuit delay optimization method in unit delay model

  • CN 106,027,032 A
  • Filed: 05/20/2016
  • Published: 10/12/2016
  • Est. Priority Date: 05/20/2016
  • Status: Active Application
First Claim
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1. RM logic circuit delay Optimization method under a unit delay model, it is characterised in that:

  • the method concrete steps include;

    Step 1, reads in boolean'"'"'s Boolean logic circuit;

    Step 2, utilizes RM expression formula simplifying method to obtain containing the simplest RM logical expression minimum with item number;

    Step 3, carries out time delay based on Huffman Huffman tree construction algorithm to each and item in the simplest RM logical expression and dividesSolve so that each minimum with the time delay of item;

    Step 4, divides being carried out time delay by all the simplest RM logical expressions formed with item based on Huffman tree construction algorithmSolve so that the time delay of the simplest RM logical expression is minimum;

    Step 5, exports the minimum time delay of the simplest RM logical expression;

    Wherein, RM implication is Reed Muller Reed-Muller.

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