Flash memory and manufacturing method thereof

Flash memory and manufacturing method thereof

  • CN 106,356,374 B
  • Filed: 07/13/2015
  • Issued: 11/27/2020
  • Est. Priority Date: 07/13/2015
  • Status: Active Grant
First Claim
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1. A method for manufacturing a flash memory is characterized by comprising the following steps:

  • providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage unit area and a peripheral circuit area;

    the memory unit area is provided with a plurality of discrete grid stacking structures of a memory transistor array and a grid stacking structure of a selection transistor, and the selection transistor is used for selecting a certain row or a certain column of memory transistors in the memory transistor array;

    the peripheral circuit area is provided with a plurality of discrete grid stacking structures of logic transistors;

    gaps between the gate stack structures of the memory transistors are smaller than gaps between the gate stack structures of the logic transistors;

    shallow ion implantation is carried out to form source-drain lightly doped regions of the storage transistor, the selection transistor and the logic transistor respectively;

    forming side walls on the side walls of the gate stack structures of the storage transistor, the selection transistor and the logic transistor, and respectively forming source-drain heavily doped regions of the storage transistor, the selection transistor and the logic transistor by deep ion implantation;

    forming a source-drain lightly doped region and a source-drain heavily doped region, wherein a buffer oxide layer covers the semiconductor substrate for ion implantation;

    after a source-drain heavily doped region is formed, a sacrificial layer is formed on the semiconductor substrate and the grid stacking structure, and the sacrificial layer completely covers the grid stacking structure;

    etching back a part of height of the sacrificial layer until the top surface and the upper part of the side wall of the gate stack structure of the memory transistor, the top surface and the upper part of the side wall of the gate stack structure of the selection transistor and the top surface and the upper part of the side wall of the gate stack structure of the logic transistor are exposed;

    removing the sacrificial layer, depositing metal on the top surface and the side wall of the exposed gate stack structure, and performing silicification to form metal silicide;

    or, firstly, depositing metal on the exposed top surface of the gate stack structure and the upper part of the side wall at a high height, and carrying out silicification, wherein the metal is simultaneously deposited on the sacrificial layer, and after the silicification, removing the non-silicified metal and all the sacrificial layer;

    the thickness of the metal deposited on the top of the grid stack structure is larger than that of the metal deposited on the side wall of the grid stack structure;

    and forming an insulating filler between and on the separated gate stack structures, wherein the insulating filler forms air gaps between the gate stack structures of the memory transistor.

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