It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source

It is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source

  • CN 107,015,595 A
  • Filed: 05/03/2017
  • Published: 08/04/2017
  • Est. Priority Date: 05/03/2017
  • Status: Active Application
First Claim
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1. one kind is operated in subthreshold region high-precision low-power consumption low-voltage bandgap reference source, it is characterised in that including:

  • Current mirror electricityRoad, produces the PTAT generation circuits of positive temperature coefficient voltage, produces the CTAT generation circuits of negative temperature coefficient voltage, linear compensationCircuit output offset, offset, positive temperature coefficient voltage and negative temperature coefficient voltage are done and, produce reference voltage VREF

    Wherein, the current mirroring circuit includes PMOS M9, PMOS M8, PMOS M13, PMOS M14 and n PMOSPipe, i.e. PMOS M101, PMOS M102 ... PMOSs M10n;

    PMOS M9, PMOS M8PMOS pipes M13, PMOS M14And the source electrode connection VDD of n PMOS;

    PMOS M8 drain electrode connection PMOS M8 grid;

    PMOS M14 drain electrode connectsConnect PMOS M14 grid;

    PMOS M9, PMOS M8, PMOS M101, PMOS M102 ... PMOSs M10n grid and first order automatic biasingThe upper strata NMOS tube M3 of stacked structure drain electrode is connected;

    The drain electrode phase of PMOS M13, PMOS M14 grid and NMOS tube M15Even;

    PMOS M9 is connected with PNP type triode Q0 emitter stage;

    PMOS M101 drain electrode and second level automatic biasing stacked structureUpper strata NMOS tube M111 drain electrode be connected;

    PMOS M102 drain electrode and the upper strata NMOS tube of third level automatic biasing stacked structureM112 drain electrode is connected;

    ... PMOS M10m drain electrode and the upper strata NMOS tube M11m of n-th grade of automatic biasing stacked structure leakageExtremely it is connected;

    PMOS M10n drain electrode is connected with the lower floor NMOS tube M12m of afterbody automatic biasing stacked structure drain electrode;

    PMOS M13 drain electrode is connected with PNP type triode Q1 emitter stage;

    PMOS M14 drain electrode and NMOS tube M15 drain electrode phaseEven;

    PTAT generation circuits include m grades of automatic biasing stacked structures, and automatic biasing stacked structures at different levels include upper strata NMOS tube and lower floorNMOS tube, the source electrode of the upper strata NMOS tube of automatic biasing stacked structures at different levels is connected with the drain electrode of lower floor'"'"'s NMOS tube;

    One-level automatic biasingThe drain electrode connection of the source electrode of lower floor'"'"'s NMOS tube of stacked structure and lower floor'"'"'s NMOS tube of previous stage automatic biasing stacked structure;

    M gradesThe upper strata NMOS tube M11m of automatic biasing stacked structure grid is connected to PMOS together with drain electrode, lower floor NMOS tube M12m gridPipe M10n drain electrode;

    The upper strata NMOS tube M111 of second level automatic biasing stacked structure drain electrode and grid, lower floor NMOS tube M121Grid all connect PMOS M101 drain electrode;

    ... the upper strata NMOS tube M11m of m grades of automatic biasing stacked structures drain electrode withGrid, lower floor NMOS tube M12m grid all connect PMOS M10m drain electrode;

    The upper strata of first order automatic biasing stacked structureNMOS tube M3 and lower floor NMOS tube M2 grid are connected to PNP type triode Q0 emitter stage together;

    First order automatic biasing is stackedThe upper strata NMOS tube M3 of structure drain electrode connection PMOS M101 drain electrode;

    Lower floor'"'"'s NMOS tube of first order automatic biasing stacked structureM2 source electrode connection NMOS tube M1 drain electrode;

    M=n-1;

    CTAT voltage circuit includes NMOS tube M3, NMOS tube M2, NMOS tube M1, PNP type triode Q0;

    PNP type triode Q0'"'"'sColelctor electrode, base stage connection ground;

    PNP type triode Q0 emitter stage connection PMOS M9 drain electrode;

    NMOS tube M3 and NMOS tube M2Grid be connected to PNP type triode Q0 emitter stage together;

    NMOS tube M3 drain electrode connection PMOS M8 drain electrode;

    NMOS tubeM3 source electrode connection NMOS tube M2 drain electrode;

    NMOS tube M1 grid and drain electrode connection NMOS tube M2 source electrode;

    NMOS tube M1'"'"'sSource ground;

    Linear compensation circuit includes NMOS tube M15, NMOS tube M16, NMOS tube M17, PNP type triode Q1;

    PNP type triode Q1Emitter stage connection PMOS M13 drain electrode, PNP type triode Q1 base stage and grounded collector;

    NMOS tube M15 and NMOS tubeM16 grid connection PNP type triode Q1 emitter stage;

    NMOS tube M15 drain electrode connection PMOS M14 drain electrode, NMOS tubeM15 source electrode connection NMOS tube M16 drain electrode;

    NMOS tube M16 source electrode connection NMOS tube M17 drain electrode;

    NMOS tube M17 gridPole and drain electrode are connected with NMOS tube M16 source electrode, NMOS tube M17 source ground.

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