The preparation method and its structure of bottom emitting type white light OLED panel

The preparation method and its structure of bottom emitting type white light OLED panel

  • CN 107,293,555 A
  • Filed: 06/19/2017
  • Published: 10/24/2017
  • Est. Priority Date: 06/19/2017
  • Status: Active Application
First Claim
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1. a kind of preparation method of bottom emitting type white light OLED panel, it is characterised in that comprise the following steps:

  • Step S1, offer underlay substrate (1) are simultaneously cleaned, and red color resistance (R), green are sequentially depositing on the underlay substrate (1)Color blocking (G) and blue color blocking (B), form color film layer (2);

    Step S2, the buffer layer (3) on the color film layer (2);

    Step S3, on the cushion (3) deposition oxide semiconductive thin film and patterned process is carried out, form oxide halfConductor layer (4 '"'"');

    Step S4, be sequentially depositing on the oxide semiconductor layer (4 '"'"') and cushion (3) insulation film (5 '"'"'), with the first gold medalBelong to layer (6 '"'"');

    Step S5, patterned process first is carried out to the first metal layer (6 '"'"'), form grid (6), then be with the grid (6)Autoregistration figure etches insulation film (5 '"'"'), forms the gate insulator (5) being located at below the grid (6);

    The grid(6) with gate insulator (5) shield portions oxide semiconductor layer (4 '"'"'), the both sides of oxide semiconductor layer (4 '"'"') are exposed;

    Step S6, the corona treatment that whole face is carried out to the oxide semiconductor layer (4 '"'"') so that the oxide is partly ledThe partial ohmic that body layer (4 '"'"') is not blocked by the grid (6) and gate insulator (5) is reduced, formation conductor layer (41), and byThe part that the grid (6) and gate insulator (5) are blocked still is semiconductor, forms semiconductor channel area (42);

    Step S7, deposit interlayer insulating film on the grid (6), conductor layer (41) and cushion (3) and (7) and carry out patternChange handle, formed through the interlayer insulating film (7) with expose respectively conductor layer (41) part surface source contact openings (71),Drain contact hole (72) and pixel definition hole (73);

    The source contact openings (71) are located at institute respectively with drain contact hole (72)The both sides of grid (6) and gate insulator (5) are stated, the pixel definition hole (73) is close to the source contact openings (71);

    Step S8, on the interlayer insulating film (7) depositing second metal layer and carry out patterned process, formed source electrode (S) andDrain (D), the source electrode (S) contacts the conductor layer (41) through the source contact openings (71), and the drain electrode (D) is through the leakagePole contact hole (72) contacts the conductor layer (41);

    The source electrode (S), drain electrode (D), grid (6), gate insulator (5), conductor layer (41) portion contacted with the source electrode (S)Conductor layer (41) part and semiconductor channel area (42) divide, contacted with the drain electrode (D) constitutes thin film transistor (TFT) (T);

    Step S9, deposit passivation layer (9) and carry out at patterning on the source electrode (S), drain electrode (D) and interlayer insulating film (7)Reason, forms the through hole (91) for exposing the pixel definition hole (73);

    Step S10, with the conductor layer (41) it is anode deposition white light OLED luminescent layer in the pixel definition hole (73)(10);

    Step S11, the deposited metal negative electrode (11) on the white light OLED luminescent layer (10) and passivation layer (9).

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