XTS AES encryptions circuit, decryption circuit and its method
XTS AES encryptions circuit, decryption circuit and its method
 CN 107,888,373 A
 Filed: 09/29/2016
 Published: 04/06/2018
 Est. Priority Date: 09/29/2016
 Status: Active Application
First Claim
1. a kind of XTSAES data cells encrypted circuit, it is characterised in that data cell includes m+1 data block P_{0}~P_{m}, m isPositive integer, wherein, 1~m data block P_{0}~P_{m1}It is respectively provided with predetermined word joint number, the m+1 data block P_{m}Byte number be less thanOr equal to predetermined word joint number；
 The XTSAES data cells encrypted circuit includes：
First ciphering unit (AES0), modular multiplication unit, XOR unit, secondCiphering unit (AES1), the 3rd ciphering unit (AES2) and caching and adjustment unit, wherein,First ciphering unit is used to the adjusted value of data cell is encrypted and exported to give modular multiplication unit；
The previous operation result of output or modular multiplication unit of the modular multiplication unit to the first ciphering unit carries out modular multiplication, and caches fortuneCalculate result；
XOR unit includes the first XOR unit, the second XOR unit and the 3rd XOR unit, wherein, the first XOR unit is used forOne of data block of output and data cell to modular multiplication unit does XOR, and the output coupling of the first XOR unit is encrypted to secondThe input of unit (AES1)；
Second XOR unit is done for the output to the second ciphering unit (AES1) and the output of modular multiplication unitXOR, the output coupling of the second XOR unit to the 3rd ciphering unit (AES2)；
3rd XOR unit is used for single to the 3rd encryptionFirst output of (AES2) does XOR with the output of modular multiplication unit；
Cache and enter with XOR result of the adjustment unit for output and the output of modular multiplication unit to the second ciphering unit (AES1)Row caching, caching are additionally operable to the data block P of splicing data cell with adjustment unit_{m}It is single with adjustment with the data block of caching, cachingThe output coupling of member is to the 3rd ciphering unit (AES2).
Chinese PRB Reexamination
Abstract
This application discloses a kind of XTS AES encryptions circuit, decryption circuit and its method, it is related to information security field, when solving available data unit CipherText Stealing computing is carried out in pipeline organization, the high technical problem of linear speed computing, complex designing difficulty can not be carried out.Data cell includes m+1 data block P_{0}~P_{m}, m is positive integer, wherein, 1~m data block P_{0}~P_{m‑1}It is respectively provided with predetermined word joint number, the m+1 data block P_{m}Byte number be less than or equal to predetermined word joint number wherein, XTS AES encryption circuits include：First ciphering unit (AES0), modular multiplication unit, XOR unit, the second ciphering unit (AES1), the 3rd ciphering unit (AES2) and caching and adjustment unit.The application is applied to encryption/decrypted transport of data cell.

8 Citations
A kind of XTSSM4 encrypted circuit of highperformance small area  
Patent #
CN 109,150,497 A
Filed 07/26/2018

Current Assignee

ENDECRYPTOR CAPABLE OF PERFORMING PARALLEL PROCESSING AND ENCRYPTION/DECRYPTION METHOD THEREOF  
Patent #
US 20110123020A1
Filed 09/02/2010

Current Assignee
N/A

MULTIPLEMODE CRYPTOGRAPHIC MODULE USABLE WITH MEMORY CONTROLLERS  
Patent #
US 20110255689A1
Filed 04/15/2010

Current Assignee
N/A

Cryptographic apparatus and memory system  
Patent #
CN 102,411,694 A
Filed 08/31/2011

Current Assignee

Low Latency Encryption and Authentication in Optical Transport Networks  
Patent #
US 20140044262A1
Filed 08/09/2012

Current Assignee
N/A

Data encryption and decryption system and method thereof  
Patent #
CN 104,852,798 A
Filed 05/11/2015

Current Assignee

Chipset with hard disk encryption function and host computer controller  
Patent #
CN 105,243,344 A
Filed 11/02/2015

Current Assignee

Data encryption/decryption method for storage apparatus  
Patent #
CN 105,354,503 A
Filed 11/02/2015

Current Assignee

10 Claims

1. a kind of XTSAES data cells encrypted circuit, it is characterised in that data cell includes m+1 data block P_{0}~P_{m}, m isPositive integer, wherein, 1~m data block P_{0}~P_{m1}It is respectively provided with predetermined word joint number, the m+1 data block P_{m}Byte number be less thanOr equal to predetermined word joint number；

The XTSAES data cells encrypted circuit includes：
First ciphering unit (AES0), modular multiplication unit, XOR unit, secondCiphering unit (AES1), the 3rd ciphering unit (AES2) and caching and adjustment unit, wherein,First ciphering unit is used to the adjusted value of data cell is encrypted and exported to give modular multiplication unit； The previous operation result of output or modular multiplication unit of the modular multiplication unit to the first ciphering unit carries out modular multiplication, and caches fortuneCalculate result； XOR unit includes the first XOR unit, the second XOR unit and the 3rd XOR unit, wherein, the first XOR unit is used forOne of data block of output and data cell to modular multiplication unit does XOR, and the output coupling of the first XOR unit is encrypted to secondThe input of unit (AES1)；
Second XOR unit is done for the output to the second ciphering unit (AES1) and the output of modular multiplication unitXOR, the output coupling of the second XOR unit to the 3rd ciphering unit (AES2)；
3rd XOR unit is used for single to the 3rd encryptionFirst output of (AES2) does XOR with the output of modular multiplication unit；Cache and enter with XOR result of the adjustment unit for output and the output of modular multiplication unit to the second ciphering unit (AES1)Row caching, caching are additionally operable to the data block P of splicing data cell with adjustment unit_{m}It is single with adjustment with the data block of caching, cachingThe output coupling of member is to the 3rd ciphering unit (AES2).


2. XTSAES data cells encrypted circuit as claimed in claim 1, it is characterised in that the processing bag to data cellInclude and correspond to data block P_{0}~P_{m}M+1 stage S_{1}~S_{m+1}。

3. XTSAES data cells encrypted circuit as claimed in claim 2, it is characterised in that
In response to the stage S of processing data block_{1}S_{m1}： First XOR unit, output and the data block (P of the current generation corresponding to data cell to modular multiplication unit_{0}P_{m2}) doXOR；
Output encryption of second ciphering unit (AES1) to the first XOR unit, the second XOR unit is to the second ciphering unit(AES1) XOR is done in output and the output of modular multiplication unit, by the stage S of the second XOR cell processing data cell_{1}To the stageS_{m1}Output exported as the 1st to the m1 that the XTSAES data cells encrypted circuit handles the data cell.

4. the XTSAES data cell encrypted circuits as described in one of claim 23, it is characterised in that
In response to the stage S of processing data block_{m}： First XOR unit, output and the data block (P of the current generation corresponding to data cell to modular multiplication unit_{m1}) do it is differentOr；
Output encryption of second ciphering unit (AES1) to the first XOR unit, (AES1) output of the second ciphering unit are supplied toThe caching and adjustment unit；
Caching is done with output of the adjustment unit to the second ciphering unit (AES1) and the output of modular multiplication unitXOR, and cache XOR result.

5. the XTSAES data cell encrypted circuits as described in one of claim 24, it is characterised in that
In response to the stage S of processing data block_{m+1}： 
By data block P_{m}The caching and adjustment unit are supplied to, the caching includes number with the data block that adjustment unit is cachedAccording to block C_{m}With data block C_{p}Two parts, the caching is with adjustment unit by data block P_{m}With data block C_{p}Merge, by the data of mergingXOR is done in the output of block and modular multiplication unit, and XOR result is supplied into the 3rd ciphering unit (AES2)； The output of 3rd ciphering unit (AES2) is supplied to the 3rd XOR unit, and the 3rd XOR unit is to the 3rd ciphering unit(AES2) XOR is done with the result of modular multiplication unit, the output of the 3rd XOR unit handles institute as the XTSAES encrypted circuitsState mth of output of data cell.


6. XTSAES data cells encrypted circuit as claimed in claim 5, it is characterised in that
Caching and adjustment unit output C_{m}, the m+ as the XTSAES data cells encrypted circuit processing data cell1 output.

7. a kind of XTSAES data cells decrypt circuit, it is characterised in that data cell includes m+1 data block C_{0}~C_{m}, m isPositive integer, wherein, 1~m data block C_{0}~C_{m1}It is respectively provided with predetermined word joint number, the m+1 data block C_{m}Byte number be less thanOr equal to predetermined word joint number；

The XTSAES data cells decryption circuit includes：
First ciphering unit (AES0), modular multiplication unit, XOR unit, secondDecryption unit (AES1), the 3rd decryption unit (AES2) and caching and adjustment unit, wherein,First ciphering unit (AES0) is used to the adjusted value of data cell is encrypted and exported to give modular multiplication unit； The previous operation result of output or modular multiplication unit of the modular multiplication unit to the first ciphering unit (AES0) carries out modular multiplication, andCache operation result； XOR unit includes the first XOR unit, the second XOR unit and the 3rd XOR unit, wherein, the first XOR unit is used forOne of data block of output and data cell to modular multiplication unit does XOR, and the output coupling of the first XOR unit is decrypted to secondThe input of unit (AES1)；
Second XOR unit is done for the output to the second decryption unit (AES1) and the output of modular multiplication unitXOR, the output coupling of the second XOR unit to the 3rd decryption unit (AES2)；
3rd XOR unit is used for single to the 3rd decryptionFirst output of (AES2) does XOR with the output of modular multiplication unit；Cache and enter with XOR result of the adjustment unit for output and the output of modular multiplication unit to the second decryption unit (AES1)Row caching, caching are additionally operable to the data block C of splicing data cell with adjustment unit_{m}It is single with adjustment with the data block of caching, cachingThe output coupling of member is to the 3rd decryption unit (AES2).


8. A kind of 8. XTSAES encrypted circuits, for being encrypted according to XTSAES agreements to data cell, it is characterised in that data sheetMember includes m+1 data block P_{0}~P_{m}, m is positive integer, and the processing to data cell includes corresponding to data block P_{0}~P_{m}'"'"'sM+1 stage S_{1}~S_{m+1}；

The XTSAES encrypted circuits include：
First AES encryption unit (AES0), the second AES encryption unit (AES1), the 3rdAES encryption unit (AES2), modular multiplication unit, the first XOR unit (101), the second XOR unit (102), the 3rd XOR unitAnd data buffer storage unit (103)；In the processing stage S of processing data unit_{1}, adjusted value encryption of the first AES encryption unit (AES0) to data cell, itsOutput coupling is to modular multiplication unit； Input of the output coupling of modular multiplication unit to the first XOR unit (101) and modular multiplication unit； First XOR unit (101) is used for output and the data block of the current generation corresponding to data cell to modular multiplication unit(P_{0}P_{m1}) do XOR； Output encryption of the second AES encryption unit (AES1) to the first XOR unit (101)； XOR is done in output of the second XOR unit (102) to the second AES encryption unit (AES1) and modular multiplication unit；
Wherein work as processingThe S of data cell_{m}During the stage, the output of the second XOR unit is cached with data buffer storage unit, the data block cached includes numberAccording to block C_{m}With data block C_{p}Two parts；
By the stage S of the second XOR cell processing data cell_{1}To stage S_{m1}Output as instituteState the 1st to the m1 output that XTSAES encrypted circuits handle the data cell；
Buffer unit caching is used for the numberAccording to the data block C of unit_{m}The m+1 output during the data cell is handled as the XTSAES encrypted circuits；Data buffer storage unit also receives in plain text, and data buffer storage unit is by data block P_{m}With data block C_{p}Merge； 3rd ciphering unit (AES2) is coupled to data buffer storage unit, the P cached to data buffer storage unit_{m}With C_{p}After mergingData are encrypted with the XOR result of the output of modular multiplication unit； XOR is done in output of the 3rd XOR unit (103) to the 3rd ciphering unit (AES2) and the output of modular multiplication unit, by the 3rdMth output of the output of XOR unit (103) as the XTSAES encrypted circuits processing data cell.


9. a kind of XTSAES decrypts circuit, for being decrypted according to XTSAES agreements to data cell, it is characterised in that data sheetMember includes m+1 data block C_{0}~C_{m}, m is positive integer, and the processing to data cell includes corresponding to data block C_{0}~C_{m}'"'"'sM+1 stage Q_{1}~Q_{m+1}；

The XTSAES decryption circuit includes：
First ciphering unit (AES0), the second decryption unit (AES1), the 3rd decryption are singleFirst (AES2), modular multiplication unit, the first XOR unit (101), the second XOR unit (102), the 3rd XOR unit (103) and dataBuffer unit；In the processing stage Q of processing data unit_{1}, adjusted value encryption of the first ciphering unit (AES0) to data cell, it is exportedIt is coupled to modular multiplication unit； Input of the output coupling of modular multiplication unit to the first XOR unit (101) and modular multiplication unit； First XOR unit (101) is used for the Q to modular multiplication unit_{1}Q_{m2}Stage exports and the Q corresponding to data cell_{1}Q_{m2}RankData block (the C of section_{0}C_{m2}) XOR is done, and for the Q to modular multiplication unit_{m}The output in stage and the Q of data cell_{m1}StageData block (C_{m1}) do XOR； Output decryption of the 2nd AES decryption units (AES1) to the first XOR unit (101)； XOR is done in output of the second XOR unit (102) to the 2nd AES decryption units (AES1) and the output of modular multiplication unit；
WhereinAs the Q of processing data unit_{m}During the stage, data buffer storage unit caches the output of the second XOR unit (102), the data cachedBlock includes data block P_{m}With data block P_{p}Two parts；
By the stage Q of second XOR unit (102) processing data unit_{1}To the stageQ_{m1}Output exported as the 1st to the m1 of data cell described in XTSAES decryption processing of circuit；
Buffer unit delaysThe data block P for the data cell deposited_{m}As the m+ described in the XTSAES decryption processing of circuit during data cell1 output；Data buffer storage unit also receives ciphertext, and data buffer storage unit is by data block C_{m}With data block P_{p}Merge； 3rd decryption unit (AES2) is coupled to data buffer storage unit, the C cached to data buffer storage unit_{m}With P_{p}After mergingData are decrypted with the XOR result of the output of modular multiplication unit； XOR is done in output of the 3rd XOR unit (103) to the 3rd decryption unit (AES2) and the output of modular multiplication unit, by the 3rdMth output of the output of XOR unit (103) as data cell described in XTSAES decryption processing of circuit.


10. XTSAES as claimed in claim 9 decrypts circuit, it is characterised in that
The modular multiplication unit includes multiple caching parts, for caching each modular multiplication result for multiple data cells, withAnd when handling the stage of the first data cell, using the modular multiplication result of the first data cell of caching as the defeated of modular multiplication unitGo out, and update with next output of the modular multiplication unit modular multiplication result of the first data cell of the caching.
Specification(s)