Coding and decoding device

Coding and decoding device

  • CN 1,134,630 A
  • Filed: 04/25/1995
  • Published: 10/30/1996
  • Est. Priority Date: 04/25/1995
  • Status: Abandoned Application
First Claim
Patent Images

1. an encoding/decoding device includes an encoder and a decoder, and wherein, encoder comprises to be had:

  • -oscillating circuit is in order to produce the required fundamental frequency of encoder;

    -phase divider, the fundamental frequency pulse signal that the output of this oscillating circuit is sent are made the phase place frequency elimination and are handled, and are sent by its output QM, the QN signal after with frequency division;

    -address array loader, by to detect 2 nThe circuit of the parallel input of individual state pin is formed;

    -rank scanning device, the QM signal of sending by phase divider and produce row and the column signal of wanting scan address array loader;

    -synchronous circuit, when and walk to after the serial follower sending a string input data, this synchronous circuit can add the output signal QM of a phase divider again at last bit of this serial data, adds the blank 1 or 2 bit times, as synchronous usefulness;

    -and walk to the serial follower, be that QM, QN signal with phase divider is with the parallel input pin of address array loader, with 2 nPlant state encoding, add the synchronizing signal of synchronous circuit, this parallel data is changed into serial data output;

    And this decoder includes;

    -oscillating circuit is in order to produce the required frequency of decoder;

    -frequency eliminator is with the fundamental frequency frequency required with the column scan device that be divided into lines;

    -address array loader is in order to detect 2 nThe parallel signal of the parallel input of state pin;

    -rank scanning device is in order to the row and the column signal of scan address array loader;

    -data string detection synchronizing signal, the data that transmitted by data input pin received code device also detect this data bits of original, will put in order string data and make Synchronous Processing;

    -counter decode circuit, inside have a counter, the rising edge of the pulse of being sent here by the data string detection synchronizing signal, and with counter reset, last positive output of counter is the output of bit;

    -comparison circuit;

    -2 nThe attitude data generator, the kind status data that it is imported the address array loader, represent that with N bit the data of decoding out with the counter decode circuit are made comparisons in comparison circuit again, compare OK is promptly exported decoded signal by its signal output part.

View all claims

    Thank you for your feedback