PLL circuit and noise reduction means for PLL circuit

PLL circuit and noise reduction means for PLL circuit

  • CN 1,162,871 A
  • Filed: 12/14/1996
  • Published: 10/22/1997
  • Est. Priority Date: 12/15/1995
  • Status: Abandoned Application
First Claim
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1. a PLL circuit comprises:

  • Voltage-controlled oscillation unit is used to produce and export the signal of the frequency of corresponding input control voltage;

    Frequency divider, by the forward position of the output signal of said voltage-controlled oscillation unit and back along in any trigger, be used for the said output signal of said voltage-controlled oscillation unit is carried out frequency division;

    Trigger equipment, by the forward position of the trigger pulse triggers that is not used as said divider device of the said output signal of said voltage controlled oscillator device and back along one of trigger, be used to obtain and export the said output signal of said frequency divider;

    The reference clock generation device is used to produce the reference clock of reference frequency;

    And phase comparison device, be used to export the output signal of corresponding said trigger equipment and the voltage of the phase difference between the said reference clock.

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