Four device sram cell with single bitline

Four device sram cell with single bitline

  • CN 1,182,535 C
  • Filed: 11/26/1997
  • Issued: 12/29/2004
  • Est. Priority Date: 12/27/1996
  • Status: Active Grant
First Claim
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1. memory cell comprises:

  • Static phase inverter with input end that links to each other with a memory node;

    This memory node is connected to the impedance of power supply;

    The first transistor with input end that links to each other with an output terminal of described static phase inverter, described the first transistor further are connected to this memory node a writing line;

    AndRespond the transistor seconds that a word line access signal is connected to this memory node an independent data bit line.

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