Method for forming wiring layer on integrated circuit with high-low topotactic area

Method for forming wiring layer on integrated circuit with high-low topotactic area

  • CN 1,248,791 A
  • Filed: 09/22/1999
  • Published: 03/29/2000
  • Est. Priority Date: 09/22/1998
  • Status: Abandoned Application
First Claim
Patent Images

1. method that on integrated circuit, forms wiring layer with height topology zone, this method may further comprise the steps:

  • In this low topology zone, but not on this high topology zone, form wiring layer;

    ThenAt least should form an insulating barrier in low topology zone;

    ThenOn this low topology zone and this high topology zone, form wiring layer on.

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