Communication interface of master-slave type processor system

Communication interface of master-slave type processor system

  • CN 1,288,201 A
  • Filed: 09/09/1999
  • Published: 03/21/2001
  • Est. Priority Date: 09/09/1999
  • Status: Abandoned Application
First Claim
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1. the communication interface in the master-slave mode multiprocessor system, it is connected primary processor and a plurality of between the processor, it is characterized in that, described have the host interface from processor, this host interface comprises address register and data register, the memory expansion mouth of one termination primary processor of described communication interface, respectively from the host interface of processor, this communication interface comprises another termination:

  • Read-write control unit, obtain address and data message from primary processor, provide access order by the requirement of host interface accessing to address decoding unit and multiselect Unit one, promptly at first the destination address from processor is given the address register of host interface, read and write the data of the data register of host interface then, and in primary processor and certain when processor communicates, it obtains address and data message from primary processor, directly by data bus with carry out address and exchanges data from processor;

    Address decoding unit obtains address information from read-write control unit, and the register address from processor host interface respectively is mapped on the corresponding address field of primary processor;

    Multiselect Unit one obtains enable signal from address decoding unit, obtains low order address information from read-write control unit then, obtains the data useful signal from primary processor simultaneously, to a plurality of from processor output data useful signal;

    Interrupt ready unit, give primary processor from a plurality of corresponding ready signal, look-at-me routes from processor, selected.

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