Method for preventing impedance of storage chip circumference from mismatching, storage system and model

Method for preventing impedance of storage chip circumference from mismatching, storage system and model

  • CN 1,411,059 A
  • Filed: 09/27/2002
  • Published: 04/16/2003
  • Est. Priority Date: 09/27/2001
  • Status: Active Application
First Claim
Patent Images

1. the wiring method of the signal line of a data/address bus, wherein:

  • Signal line comprises first lead that is placed on first terminal block and second lead that is placed at least one second terminal block;

    Second terminal block is installed on first terminal block and connects first and second leads so that be one another in series, thereby sets up signal line;

    AndAt least one semiconductor device is connected with second lead,The method comprising the steps of, and the lead that connects up is determined the impedance of this lead according to the additional capacity as the second terminal block semiconductor-on-insulator device of second lead, so that coordinate the impedance of first terminal block and the impedance of second terminal block.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×