Method and circuit for reducing leakage of grid under the state of dormancy

Method and circuit for reducing leakage of grid under the state of dormancy

  • CN 1,507,048 A
  • Filed: 12/11/2003
  • Published: 06/23/2004
  • Est. Priority Date: 12/12/2002
  • Status: Active Application
First Claim
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1. one kind is used for alleviating the method that transistor gate is sewed under resting state, comprises following steps:

  • Under described resting state to the one or more input patterns that apply in more than first device in the circuit;

    AndRespond the described of described input pattern and apply, source electrode, grid and the drain electrode end of each in the great majority in described more than first device in described circuit produce essentially identical voltage, sew thereby alleviate transistor gate.

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