Laminated integrated circuit memory

Laminated integrated circuit memory

  • CN 1,525,485 B
  • Filed: 04/03/1998
  • Issued: 12/05/2012
  • Est. Priority Date: 04/04/1997
  • Status: Active Grant
First Claim
Patent Images

1. layered integrated circuit memory, it comprises:

  • First substrate, be formed with on it memory circuitry with comprise in the circuit of steering logic any one;

    Be bonded to second substrate on said first substrate;

    Thereby between said first substrate and said second substrate, form perpendicular interconnection, wherein said second substrate be formed with on it another person in circuit that said memory circuitry and said comprises steering logic through attenuate, soft substrate basically;

    Clean stress is lower than 5 * 10 8Dyne/cm 2Dielectric layer;

    Wherein, penetrate said perpendicular interconnection one of at least in said first substrate and said second substrate comprising one of at least in said first substrate and said second substrate;

    Wherein, forming one of at least in said first substrate and said second substrate from semiconductor wafer or its part.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×