Sense mechanism for microprocessor bus inversion

Sense mechanism for microprocessor bus inversion

  • CN 1,664,800 A
  • Filed: 03/01/2005
  • Published: 09/07/2005
  • Est. Priority Date: 03/02/2004
  • Status: Active Application
First Claim
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1. , the anti-phase sense mechanism of a kind of data bus is characterized in that, comprises:

  • One first memory assembly is stored the bus positions of last bus cycles;

    AndOne analog adder, the bus position in the one present bus cycles of comparison and this bus position of these last bus cycles, and provide one to point out whether bus has this bus position over half to change a data inversion signal of state.

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