Add Q carrying system, carrying line digital engineering method computer technical scheme
Add Q carrying system, carrying line digital engineering method computer technical scheme
 CN 1,776,606 B
 Filed: 11/07/2005
 Issued: 08/27/2014
 Est. Priority Date: 11/08/2004
 Status: Active Grant
First Claim
1. one kind increases Q system, carry row computing machine;
 Comprise;
input logic (101), cpu central processing unit (102), external memory (103), output logic (104), control desk (105), output conversion logic (108), { Q} →
{ Q ^{Δ}conversion logic (109) composition;
Wherein, cpu central processing unit (102) is made up of internal memory (106), increasing Q s operation control logic (107);
Increasing Q s operation control logic (107) is made up of the heavy arithmetical unit of 2K (202) and controller (201);
Wherein the heavy arithmetical unit of 2K (202) is by the 1st of the heavy arithmetical unit of 2K, the 2nd ... i position ... composition;
I is ordinal number;
" the heavy arithmetical unit i of 2K position " is by totalizer ∑
_{i}and register net (311), the net that liquidates (312), draw Q net (313) composition (304);
Or, do not adopt the net that liquidates (312) and draw Q net (313);
The wherein said net that liquidates (312) is patrolled and examined by the logic that liquidates (305);
Or be connected to form by each register two or two in the individual logic that liquidates of K (2K1) (305,306,307) and register net (311);
The Q net (313) of drawing is is wherein patrolled and examined by one stroke of Q logic (308);
Or be connected to form by each register two or two in individual stroke of Q logic of K (2K1) (308,309,310) and register net (311);
The logic that liquidates wherein, by 1 register 1i (301), 2 register 2i (302), with _{1}logic (403), different logic (404) and with _{1}door (405) composition;
Stroke Q logic wherein, by 1 register 1i (301), 2 register 2i (302), Q value decision logic (501), with _{2}logic (502) and with _{2}door (503) composition;
If K common Q system number participates in plus and minus calculation, the integer that K is>
=2, Q is natural number;
Become 2K to increase Q system number these number conversions;
Common Q system number input { Q} →
{ Q ^{Δ}conversion logic (109) acquisition increasing Q system number;
Increase Q system number through input logic (101) to the heavy arithmetical unit of 2K (202);
In the heavy arithmetical unit of 2K (202), increase Q system number through the heavily result of computing acquisition increasing Q system number of 2K;
Then, output conversion logic (108), to increase Q system number or common Q system number, is exported by output logic (104);
Controller (201) coordinates to control increasing Q s operation control logic (107).
Litigations
Chinese PRB Reexaminations
Abstract
The invention relates to a digital engineering method and a computer filed, providing a novel digital engineering method, thereby obviously increasing the computing speed and greatly decreasing the error rate of manual computation. The invention adopts a method of increasing Qary base, carry set: K normal Qary numbers are converted into K or K or 2K increasing Qary numbers; and then the K or K or 2K increasing Qary numbers are summated. Each number is accomplished bit by bit from the least significant bit or each bit, and then the summation is counted into a next computing layer, besides, the obtained increasing Qary numbers is stored into the next computing layer or into the vacancy or 0 position of any datarow neighboring high significant bit not yet computed of the right computing layer. The computations are accomplished iteratively till only one number of the computing layer is obtained after being computed. The last number is the summation of the bias Qary base method. The invention also provides a technical proposal of increasing Qary and carry set computer.
5 Claims

1. one kind increases Q system, carry row computing machine;
 Comprise;
input logic (101), cpu central processing unit (102), external memory (103), output logic (104), control desk (105), output conversion logic (108), { Q} →
{ Q ^{Δ}conversion logic (109) composition;
Wherein, cpu central processing unit (102) is made up of internal memory (106), increasing Q s operation control logic (107);
Increasing Q s operation control logic (107) is made up of the heavy arithmetical unit of 2K (202) and controller (201);
Wherein the heavy arithmetical unit of 2K (202) is by the 1st of the heavy arithmetical unit of 2K, the 2nd ... i position ... composition;
I is ordinal number;
" the heavy arithmetical unit i of 2K position " is by totalizer ∑
_{i}and register net (311), the net that liquidates (312), draw Q net (313) composition (304);
Or, do not adopt the net that liquidates (312) and draw Q net (313);
The wherein said net that liquidates (312) is patrolled and examined by the logic that liquidates (305);
Or be connected to form by each register two or two in the individual logic that liquidates of K (2K1) (305,306,307) and register net (311);
The Q net (313) of drawing is is wherein patrolled and examined by one stroke of Q logic (308);
Or be connected to form by each register two or two in individual stroke of Q logic of K (2K1) (308,309,310) and register net (311);The logic that liquidates wherein, by 1 register 1i (301), 2 register 2i (302), with _{1}logic (403), different logic (404) and with _{1}door (405) composition;
Stroke Q logic wherein, by 1 register 1i (301), 2 register 2i (302), Q value decision logic (501), with _{2}logic (502) and with _{2}door (503) composition;
If K common Q system number participates in plus and minus calculation, the integer that K is>
=2, Q is natural number;
Become 2K to increase Q system number these number conversions;
Common Q system number input { Q} →
{ Q ^{Δ}conversion logic (109) acquisition increasing Q system number;
Increase Q system number through input logic (101) to the heavy arithmetical unit of 2K (202);
In the heavy arithmetical unit of 2K (202), increase Q system number through the heavily result of computing acquisition increasing Q system number of 2K;
Then, output conversion logic (108), to increase Q system number or common Q system number, is exported by output logic (104);
Controller (201) coordinates to control increasing Q s operation control logic (107).
 Comprise;

2. the computing machine of claim 1, is characterized in that, adopts " twodimentional computing " in the heavy arithmetical unit of 2K (202);
 , number everybody on carry out computing simultaneously;
And each number on each, also carries out elder generation simultaneously and " liquidates ", " draws Q " afterwards, " adds up ";
In the time that next operation layer instruction arrives, carry digit and " stepbystep and " number are added again;
So repeat, until in operation layer, till only obtaining a number after computing;
Finally, then through totalizer ∑
_{i}(304) the output number of suing for peace;
In the time adopting complete one yard of coding, abovementioned " twodimentional computing " is " threedimensional computing ";
In the time adopting " liquidating " and " draw Q ", the instruction of being sent by controller is carried out computing on everybody of number simultaneously;
And each number on each, also carries out elder generation simultaneously and " liquidates ", " draws Q " afterwards, " adds up ";
Cumulative adopt " most totalizer ";
In the time adopting common two number " totalizer ", order serial is cumulative;
Wherein totalizer ∑
_{i}(304) be each with a sign bit, with 2K _{i}the corresponding totalizer of register (303);
In the time adopting complete one yard of coding, the totalizer ∑
in the heavy arithmetical unit of 2K (202) _{i}(304) economize slightly complete one yard of shift register.
 , number everybody on carry out computing simultaneously;

3. the computing machine of claim 2, is characterized in that, wherein said register net (311) is made up of 2K register;
 Each register two or two is connected;
2K register deposited 2K and increased Q system number;
Totalizer ∑
_{i}(304) be and the corresponding totalizer of 2K register 2Ki (303), be used for depositing cumulative sum number;
Each register and totalizer ∑
_{i}(304) each is distributed a sign bit, and this sign bit is common two condition trigger;
Sign bit or be placed in special sign bit register is to deposit to increase the register of Q system number or each of totalizer is distributed a symbol in the time of computing.
 Each register two or two is connected;

4. the computing machine of claim 1, is characterized in that, further comprises:
 1 register 1i (301) and 2 register 2i (302), with sign bit, are common two condition trigger before it;
When adopting complete one yard when encoding and adopting twovalue components and parts, 1 register 1i (301), complete one is encoded to 1i1 position, 1i2 position (401);
2 register 2i (302), complete one is encoded to 2i1 position, 2i2 position (402);
2K register 2Ki (303), complete one is encoded to 2Ki1 position, 2Ki2 position;
From 1 _{i}1,1 _{i}2 and 2 _{i}1,2 _{i}2, until 2Ki1,2Ki2, in complete one yard of coding all, appoint and get two and form combination;
1 register 1i (301) and 2 register 2i (302), with sign bit, are common two condition trigger before it;
When adopting complete one yard when encoding and adopting twovalue components and parts, 1 register 1i (301), complete one is encoded to 1i1 position, 1i2 position (401);
2 register 2i (302), complete one is encoded to 2i1 position, 2i2 position (402);
2K register 2Ki (303), complete one is encoded to 2Ki1 position, 2Ki2 position;
From 1 _{i}1,1 _{i}2 and 2 _{i}1,2 _{i}2, until 2Ki1,2Ki2, in complete one yard of coding all, appoint and get Q and form and combine.
 1 register 1i (301) and 2 register 2i (302), with sign bit, are common two condition trigger before it;

5. the computing machine of claim 1, is characterized in that, wherein increases Q system number and does not encode;
 Or to increase Q system number encoder;
Or encode with complete one yard;
Its complete one yard of compiling is determined code length or is become code length.
 Or to increase Q system number encoder;
Specification(s)