Heterogeneous processors sharing a common cache

Heterogeneous processors sharing a common cache

  • CN 1,783,033 B
  • Filed: 11/18/2005
  • Issued: 07/27/2011
  • Est. Priority Date: 11/19/2004
  • Status: Active Grant
First Claim
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1. heterogeneous processor system comprises:

  • Bridge;

    Be coupled to first multi-core processor of bridge, comprise the heterogeneous processor kernel that is arranged in after the shared cache and is connected to shared cache;

    Be coupled to second processor of bridge, comprise at least one processor cores and the local cache that is connected to this at least one processor cores;

    AndBe coupled to the primary memory of bridge;

    Wherein data are by the reading and write from a processor cores and be sent to another processor cores of high-speed cache, and do not need to load primary memory.

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