Method and apparatus for a low jitter dual-loop fractional N-type synthesizer

Method and apparatus for a low jitter dual-loop fractional N-type synthesizer

  • CN 1,784,831 A
  • Filed: 05/03/2004
  • Published: 06/07/2006
  • Est. Priority Date: 05/02/2003
  • Status: Active Application
First Claim
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1. , a kind of device, comprising:

  • First phase-locked loop (PLL) circuit comprises the input that is used to receive timing reference signal, the controllable oscillator circuit that oscillator output signal is provided and multimode feedback divider circuit;

    WithThe second control loop circuit, it selectively is coupled to provide controlling value to described multimode feedback divider circuit, controls described oscillator output signal thus.

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