Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements

Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements

  • CN 1,826,670 B
  • Filed: 07/15/2004
  • Issued: 12/05/2012
  • Est. Priority Date: 07/23/2003
  • Status: Active Grant
First Claim
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1. comprise a plurality of layers semiconductor device (10), this semiconductor device (10) comprising:

  • Substrate (20) with first first type surface,The inductance element of on said first first type surface of this substrate (20), making (11), this inductance element (11) comprises at least one lead,A plurality of tiling structures in one deck at least,Wherein these a plurality of tiling structures are electrically connected, and are arranged to geometrical pattern (14), cause image current so that be suppressed at basically in the said tiling structure by the electric current in the said inductance element (11),Wherein this tiling structure is formed in the zone outside the direct zone below said inductance element (11), andWherein said semiconductor device (10) also comprises capacity cell (100);

    This capacity cell (100) comprises two electrode for capacitors (101,102);

    In the said electrode for capacitors at least one formed by a plurality of tiling structures, and the distance between said capacity cell and the said inductance element is bigger 50 times than minimum metal width at least.

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