Low stress sidewall spacer in integrated circuit technology

Low stress sidewall spacer in integrated circuit technology

  • CN 1,902,743 A
  • Filed: 12/21/2004
  • Published: 01/24/2007
  • Est. Priority Date: 01/12/2004
  • Status: Active Application
First Claim
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1. method (900) that forms integrated circuit, it comprises:

  • Semiconductor substrate (102) is provided;

    Form gate dielectric (104) on this Semiconductor substrate (102);

    Form grid (106) on this gate dielectric (104);

    Form several source/drain junctions (304) (306) in this Semiconductor substrate (102);

    Use the low power plasma enhanced chemical vapor deposition process, form sidewall spacer (402) on every side in this grid (106);

    Form silicide (604) (606) (608) on this source/drain junctions (304) (306) and this grid (106);

    Deposition interlayer dielectric (702) is in this Semiconductor substrate (102) top;

    AndForm several to the contact (802) (804) (806) of this silicide (604) (606) (608) in this interlayer dielectric.

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