Subcarrier-controlled wireless frequency-modulation remote addressing broadcasting system

Subcarrier-controlled wireless frequency-modulation remote addressing broadcasting system

CN
  • CN 202,261,318 U
  • Filed: 10/24/2011
  • Issued: 05/30/2012
  • Est. Priority Date: 10/24/2011
  • Status: Active Grant
First Claim
Patent Images

1. the long-range addressable broadcast of the wireless frequency modulation system of subcarrier control, there are the main circuit of subcarrier sc A encoder circuit, receiving terminal, the high frequency receiving circuit of receiving terminal in the long-range addressable broadcast of the wireless frequency modulation system of this subcarrier control, it is characterized in that:

  • Subcarrier sc A encoder circuit comprises the hand-coding circuit;

    The input of hand-coding circuit (P2.0) links to each other with the output (P2.0) of computer code'"'"'s circuit of communicating by letter through serial communication circuit;

    The output of hand-coding circuit (PZW1) links to each other with the input (PZW1) of modulated subcarrier signal loaded circuit;

    The output (netlc2-1) of the subcarrier generation modulation circuit of two signal frequencies joins with the input (netlc2-1) of subcarrier signal buffer amplifier circuit;

    The input (PZW2) of the subcarrier generation modulation circuit of two signal frequencies joins with the output (PZW2) of computer code'"'"'s circuit of communicating by letter through serial communication circuit;

    The input of subcarrier signal buffer amplifier circuit (Y25) joins with the output (Y25) of the subcarrier generation modulation circuit of two signal frequencies;

    The output of subcarrier signal buffer amplifier circuit (netc460-2) joins with the input (netc460-2) of modulated subcarrier signal loaded circuit, and the input (Y17) of modulated subcarrier signal loaded circuit joins with the output (Y17) of modulated subcarrier signal loaded circuit;

    The main circuit of receiving terminal comprises control audio amplifier power supply switching circuit;

    The input (TXD) of control audio amplifier power supply switching circuit is connected with the output (TXD) of watchdog circuit;

    The input (ZSD-2) of control audio amplifier power supply switching circuit is connected with the output (ZSD-2) of the DC power supply 16V rectification circuit of the main circuit of receiving terminal;

    The input (YY1) of the SCA signal first order buffer amplifier circuit of the demodulation of the main circuit of receiving terminal is connected with the output (YY1) that receives high frequency plate connecting interface socket with motherboard circuit;

    The input (1-13) of the SCA signal first order buffer amplifier circuit of demodulation is connected with the output (1-13) that with AT89S52 is the single-chip microcomputer decoding control circuit at center, and the output (1-15) of the SCA signal first order buffer amplifier circuit of demodulation is connected with the input (1-15) that with AT89S52 is the single-chip microcomputer decoding control circuit at center;

    The motherboard circuit of receiving terminal main circuit is connected with the output (A-R) of the demodulation circuit of intermediate frequency of the high frequency receiving circuit of receiving terminal with the input (YY2) that receives high frequency plate connecting interface socket;

    Motherboard circuit puts with the height of the high frequency receiving circuit of receiving terminal with the output (P1.5) that receives high frequency plate connecting interface socket and the input (NetlC4_16) of local oscillator phase-locked loop control circuit is connected;

    Motherboard circuit puts with the height of the high frequency receiving circuit of receiving terminal with the output (P1.4) that receives high frequency plate connecting interface socket and the input (NetR112_2) of local oscillator phase-locked loop control circuit is connected, the output (NETC42-2) of motherboard circuit and reception high frequency plate connecting interface socket and receiving terminal main circuit be that the input (NETC42-2) of audio power amplifier circuit of watchdog circuit, the receiving terminal main circuit of single-chip microcomputer decoding control circuit, the receiving terminal main circuit at center is connected with AT89S52;

    The receiving terminal main circuit be that the output (1-13) of the single-chip microcomputer decoding control circuit at center is connected with the input (1-13) of the SCA signal first order buffer amplifier circuit of the demodulation of receiving terminal main circuit with AT89S52;

    The output (1-15) of the SCA signal first order buffer amplifier circuit of the demodulation of receiving terminal main circuit and receiving terminal main circuit be that the input (1-15) of the single-chip microcomputer decoding control circuit at center is connected with AT89S52;

    The output (NetL11) that with AT89S52 is the single-chip microcomputer decoding control circuit at center is connected with the input (NetL11) of watchdog circuit, is that the output (P1.3) of the single-chip microcomputer decoding control circuit at center is connected with the input (P1.3) of the keyboard control circuit of receiving terminal main circuit with AT89S52;

    The input of keyboard control circuit (P1.2) is connected with the output (P1.2) that with AT89S52 is the single-chip microcomputer decoding control circuit at center;

    The high frequency receiving circuit of receiving terminal comprises demodulation circuit of intermediate frequency;

    The output of demodulation circuit of intermediate frequency (QQ32) is connected with the input (YY1) that receives high frequency plate connecting interface socket with motherboard circuit;

    The output of demodulation circuit of intermediate frequency (y1) is connected with the input (O2) that receives high frequency plate connecting interface socket with motherboard circuit, and demodulation circuit of intermediate frequency is connected with the input (01) that receives high frequency plate connecting interface socket with motherboard circuit with output (y3).

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