The inductance substrate isolation structure of integrated circuit

The inductance substrate isolation structure of integrated circuit

  • CN 203,967,076 U
  • Filed: 06/26/2014
  • Issued: 11/26/2014
  • Est. Priority Date: 06/26/2014
  • Status: Active Grant
First Claim
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1. an inductance substrate isolation structure for integrated circuit, is characterized in that, comprising:

  • P-type substrate;

    The N-shaped well region forming in described p-type substrate, described N-shaped well region comprises multiple n traps;

    In described multiple n traps, inject the multiple p-types active area forming;

    Wherein, described N-shaped well region is rectangle, and described N-shaped well region is divided into four delta-shaped regions by the diagonal of described N-shaped well region, equidistant parallel being distributed on each delta-shaped region between multiple described p-types active area;

    The orientation of the p-type active area on two relative delta-shaped regions is identical, and the orientation of the p-type active area on two adjacent delta-shaped regions is mutually vertical;

    Cover the polysilicon screen on described N-shaped well region, described polysilicon screen comprises many N-shaped polysilicons, and every N-shaped polysilicon covers between adjacent two n traps, and spaced apart by described p-type active area;

    Cover the metal level on described polysilicon screen, described metal level is X-type metal structure, and described X-type metal structure is arranged on the diagonal positions of described N-shaped well region;

    Cover the inductance on described metal level, the central point of described inductance overlaps with the central point of described X-type metal structure.

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