A method of fabricating an integrated circuit comprising the steps of: patterning a dielectric layer to form holes which expose the underlying material, said exposed underlying material comprises an electrically conducting material; depositing a glue layer covering said dielectric and said exposed underlying material; depositing a tungsten layer by chemical vapor deposition, said tungsten layer covering said glue layer on said dielectric and said exposed material; CHARACTERIZED IN THAT said glue layer comprises at least one member selected from the group consisting of conducting nitrides. view more

A method as recited in claim 1 in which said material comprises said silicon surface.

A method as recited in claim 1 in which said material comprises a metallic silicide.

A method as recited in claim 1 further comprising etching said tungsten and said glue layer to form a planar surface of said dielectric and said tungsten in said hole, said tungsten being etched before said glue layer.

A method as recited in claim 4 in which said conducting nitride consists essentially of TiN.

A method as recited in claim 1 in which said dielectric comprises silicon dioxide.

A method as recited in claim 1 further comprising the step of patterning said tungsten and said glue layer.