Apparatus for transferring data between a bus master and a plurality of memory locations at respective addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising: means for sequentially transferring at least three data units between said bus master and said secondary memory beginning at a first starting memory location address in said secondary memory address space and continuing sequentially beyond an l-byte boundary of said secondary memory address space; and means for, prior to completion of the transfer of the first data unit beyond said l-byte boundary, determining whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being the line of said secondary memory which includes said first data unit beyond said l-byte boundary, said means for sequentially transferring, transferring all of said data units at a constant rate. view more