Semiconductor structure and fabrication method thereof

• US 10,002,869 B2
• Filed: 04/24/2017
• Issued: 06/19/2018
• Est. Priority Date: 07/07/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Zhou, Fei
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US15/494,691
• Publication Number:
  US 20180012888A1
• Time in Patent Office: 421 Days
• Field of Search: 438156, 438173, 438192, 438212, 438268, 257220, 257263, 257328, 257330, 257331
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins; and performing a thermal annealing process.

Claims

1. A method for fabricating a semiconductor structure, comprising:

providing a plurality of fins on a semiconductor substrate;

forming an anti-diffusion layer, containing anti-diffusion ions, in the fins;

forming an anti-punch through layer after forming the anti-diffusion layer, containing anti-punch through ions, in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins; and

performing a thermal annealing process.

2. The method according to claim 1, wherein:

the anti-diffusion ions include one or more of C ions, Ge ions and N ions.

3. The method according to claim 1, wherein:

a thickness of the anti-diffusion layer is in a range of approximately 10 Å

-50 Å

.

4. The method according to claim 1, wherein forming the anti-diffusion layer comprises:

forming initial isolation structures with top surfaces below top surfaces of the fins; and

performing an anti-diffusion ion implantation process on the initial isolation structures.

5. The method according to claim 4, wherein:

an implanting dosage of the anti-diffusion ion implantation process is in a range of approximately 1.0×

10¹³ atoms/cm² 1.0×

10¹⁶ atoms/cm²; and

an implanting energy of the anti-diffusion ion implantation process is in a range of approximately 1 KeV-30 KeV.

6. The method according to claim 4, wherein forming the anti-punch through layer in the fins comprises:

removing a partial thickness of the initial isolation structures to form isolation structures; and

performing an anti-punch through ion implantation process on the isolation structures.

7. The method according to claim 6, wherein:

the anti-punch through ions are carbon ions;

an implanting energy of the anti-punch through ion implantation process is in a range of approximately 1.0×

10¹³ atoms/cm² 1.0×

10¹⁵ atoms/cm²; and

an implanting energy is in a range of approximately 5 KeV-100 KeV.

8. The method according to claim 6, wherein:

the partial thickness is in a range of approximately 15 Å

-60 Å

.

9. The method according to claim 1, before forming the anti-diffusion layer and the anti-punch through layer, further comprising:

forming isolation structures on the semiconductor substrate, a top surface of the isolation structures being below top surfaces of the fins.

10. The method according to claim 9, wherein forming the anti-punch through layer comprises:

performing an anti-punch through ion implantation process to the isolation structures.

11. The method according to claim 9, further comprising:

forming a doping layer having anti-diffusion ions on the isolation structures.

12. The method according to claim 11, wherein:

the doping layer is formed by a chemical vapor deposition process; and

the anti-diffusion ions are doped during the chemical vapor deposition process.

13. The method according to claim 11, wherein:

the doping layer is made of silicon oxide having the anti-diffusion ions.

14. A semiconductor structure, comprising:

a plurality of fins formed on a semiconductor substrate;

a plurality of isolation structures formed between adjacent fins on the semiconductor substrate;

an anti-diffusion layer, containing anti-diffusion ions, formed in the fins, wherein top surfaces of the isolation structures are coplanar with a bottom surface of the anti-diffusion layer; and

an anti-punch through layer, containing anti-punch through ions, formed in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins.

15. The semiconductor structure according to claim 14, wherein:

the anti-punch through ions include one or more type of C ions, Ge ions and N-type ions.

16. The semiconductor structure according to claim 14, wherein:

a thickness of the anti-diffusion layer is in a range of approximately 10 Å

-50 Å

.

17. The semiconductor structure according to claim 14, wherein:

a concentration of the anti-diffusion ions in the anti-diffusion layer is in a range of approximately 1.0×

10¹³ atoms/cm² 1.0×

10¹⁶ atoms/cm².

18. The semiconductor structure according to claim 14, further comprising:

isolation structures formed on the base substrate among the fins.

19. A semiconductor structure, comprising:

a plurality of fins formed on a semiconductor substrate;

an anti-diffusion layer, containing anti-diffusion ions, formed in the fins; and

an anti-punch through layer, containing anti-punch through ions, formed in the fins, a top surface of the anti-punch through layer being below a top surface of the anti-diffusion layer, and the anti-diffusion layer preventing the anti-punch through ions from diffusing toward tops of the fins, wherein;

a thickness of the anti-punch through layer is in a range of approximately 20 Å

-60 Å

;

the anti-punch through ions are one of P ions, As ions, B ions and F ions;

a concentration of the anti-punch through ions is in a range of approximately 1.0×

10¹³ atoms/cm² 1.0×

10¹⁵ atoms/cm².

20. The semiconductor structure according to claim 19, wherein:

the anti-punch through ions include one or more type of C ions, Ge ions and N-type ions.