Semiconductor structure with multiple transistors having various threshold voltages

• US 10,014,387 B2
• Filed: 02/18/2016
• Issued: 07/03/2018
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Zhao, Dalong, Bakhishev, Teymur, Scudder, Lance, Gregory, Paul E., Duane, Michael, Sridharan, U. C., Ranade, Pushkar, Shifren, Lucian, Hoffmann, Thomas
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/047,052
• Publication Number:
  US 20160163823A1
• Time in Patent Office: 866 Days
• Field of Search: 438276, 438391, 438402
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Claims

1. A method of fabricating a semiconductor structure, comprising:

concurrently implanting in a substrate a first screening region for each of first, second, and third transistor elements;

implanting in the substrate a second screening region above the first screening region for the second transistor element;

implanting in the substrate a third screening region above the first screening region for the third transistor element;

forming a substantially undoped epitaxial layer covering the first, second, and third screening regions to form a channel layer for each of first, second, and third transistor elements,

wherein the first screening region is in contact with at least one of the second and third screening regions.

2. The method of claim 1, wherein the first screening region is separated from at least one of the second and third screening regions.

3. The method of claim 1, wherein a dopant concentration of the first screening region is higher than each of a dopant concentration of the second screening region and a dopant concentration of the third screening region different from the dopant concentration of the second screening region.

4. The method of claim 1, wherein the third screening region is implanted at a lesser depth than the second screening region.

5. The method of claim 1, wherein:

the channel layer on the substrate for each of the first, second, and third transistor elements is formed by a blanket epitaxial growth.

6. The method of claim 1, further comprising:

concurrently implanting a first antipunchthrough region for each of the first, second, and third transistor elements;

concurrently implanting a second antipunchthrough region above the first antipunchthrough region for each of the first, second, and third transistor elements;

wherein the first and second antipunchthrough regions underlie the respective screening regions of the first, second, and third transistor elements.

7. The method of claim 6, wherein the first antipunchthrough region is formed in contact with the second antipunchthrough region.

8. The method of claim 6, wherein the second antipunchthrough region is formed in contact with the first screening region.

9. The method of claim 1, wherein each of the transistor elements has a gate with a source and a drain on either side of the gate, each of the first and second screening regions extends laterally across the length of the channel and abuts the source and drain.

10. The method of claim 9, wherein each of the first and second screening regions is located to be below the surface of the substrate at a distance of at least less than 1/1.5 times a length of the gate and above the bottom of the source and drain to which each of the screening regions abuts.